Re: [Xen-devel] [PATCH v3 6/9] viridian: add implementation of synthetic interrupt MSRs

[Wei Liu <wei.liu2@xxxxxxxxxx>]

On Thu, Jan 31, 2019 at 10:47:27AM +0000, Paul Durrant wrote:
> This patch introduces an implementation of the SCONTROL, SVERSION, SIEFP,
> SIMP, EOM and SINT0-15 SynIC MSRs. No message source is added and, as such,
> nothing will yet generate a synthetic interrupt. A subsequent patch will
> add an implementation of synthetic timers which will need the infrastructure
> added by this patch to deliver expiry messages to the guest.
> 
> NOTE: A 'synic' option is added to the toolstack viridian enlightenments
>       enumeration but is deliberately not documented as enabling these
>       SynIC registers without a message source is only useful for
>       debugging.
> 
> Signed-off-by: Paul Durrant <paul.durrant@xxxxxxxxxx>
> ---
> Cc: Ian Jackson <ian.jackson@xxxxxxxxxxxxx>
> Cc: Wei Liu <wei.liu2@xxxxxxxxxx>
> Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Cc: George Dunlap <George.Dunlap@xxxxxxxxxxxxx>
> Cc: Jan Beulich <jbeulich@xxxxxxxx>
> Cc: Julien Grall <julien.grall@xxxxxxx>
> Cc: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
> Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>
> Cc: Tim Deegan <tim@xxxxxxx>
> Cc: "Roger Pau Monné" <roger.pau@xxxxxxxxxx>
> 
> v3:
>  - Add the 'SintPollingModeAvailable' bit in CPUID leaf 3
> ---
>  tools/libxl/libxl.h                    |   6 +
>  tools/libxl/libxl_dom.c                |   3 +
>  tools/libxl/libxl_types.idl            |   1 +

For the toolstack part:

Acked-by: Wei Liu <wei.liu2@xxxxxxxxxx>

Sorry I don't have time to go through the viridian spec, but the rest
looks sensible to me.

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