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Re: [Xen-devel] [PATCH v2] x86/atomic: Improvements and simplifications to assembly constraints
- To: Jan Beulich <JBeulich@xxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Mon, 18 Mar 2019 14:11:06 +0000
- Autocrypt: addr=andrew.cooper3@xxxxxxxxxx; prefer-encrypt=mutual; keydata= mQINBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABtClBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPokCOgQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86LkCDQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAYkC HwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA==
- Cc: Xen-devel <xen-devel@xxxxxxxxxxxxx>, Wei Liu <wei.liu2@xxxxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Delivery-date: Mon, 18 Mar 2019 14:14:22 +0000
- Ironport-data: A9a23:tZM0Xq2VkeA8xbEPSPbDix16xcxjqk9dZdB6A9l9DSB0Rhpb0RKMlP kp+9CvfA2cHJTjMZiPyj+TsYtub1wQJeThKwmnKVxU9zfLNUt+wCp5lIF9Nd+IIXp+PtQHMj vIjVI8N/EbdHUmxkYnL9zWTCnXdO2ZCZtm/kKu2787vy5Ys2cczIke4L20t5Gs1ddnmYHBBC ter5cmVGi7qyC01v7iLi+O3dh/5oAV9J3Zj4c8KqOMSCoT5x6t5N7elCOHQisVKGlLG2WuCm Px/SBorUU2FJ5BbYSazy3uv6E2Lje+EBhkwJtv2ZuswK5icBU6/dnoKcyBawhqYX02fHd23Z Zc0uWps5Wfp8Ok5SNJCNxma1MAcyzgLZRt6wKXlpeewyJQsGhfkBhjFh9wRFS0Y1eLbqeRHC GnESI3q2R0MmGAq/FR7Ed7uiY7eL0Qnczxo1u1uvbWlXsCDleBaqu1NiCGM2cy3CI3zdnh+B wivP6xmYpCFBr4Jq2KN1C+Z0kVFRqe3FRZUtQWw0iCoTLxmQ/KYwtehgYKTExoRqhG8fABgy qo+mkS+Ld4DPjf8HsmBxvJ79IU1o8Z46wQOzekZG7wHEB+ZtkMJHMiyLI1CVtPosGWVootz7 Z9s0EKgxB2VnOt/Wb7XLCJodV4eKhPVHoI5t9T6WcLPqnZnBPIDR1qNmFjjaYk7ikZHEoPWh +UKqGbKImXeLkWxExNBZnOxCZ/EIeoiAyezgqSURQ+b6kEgbPDYXfavwPbLbhxaWZgkhIUtQ dFH4etQDacBxcYkWs4istqZUApJ1v6GUWgdOGZiNpGJN1a8IBaEDioxG9Of0cU8JtnRkAGAp /LGl5ZZ0Q0R3dH6BI9yg6/6IkTr/D3DxLUJkVLxA0B1u3UOGqI8uM8vk/zHqR4O8b6MQ3TMJ iPDUUlR+X45hWgMZEHpzV74Ww4gooi+MG9SoZeV/arejDUrR6eFjEhnC//qxUIbjD7IVemBv Q4K0PFCjm4p0XjKDW2tqzkXG1N0h8dXw3D7/hs638RFbdvLCMNNizI2874/pYVHaQo1JXa4/ X8esVk+b1ATLBV3kGcSuaUm+iSZNLhXmaeXJrurMdnXvjV4HZHkhwmHPJ3k3dsV/fNFfb2/o jYs1hBrMM2+wrNBFgKE878wBR29UlbhdFVp09y4DJ0EIkLPOe9Sy9LmgDa9HX3ehcUJgiIz5 ypFJB6dEootaSSV8OYRP6ZvohKIzEI7ooDE1p9ZVErfv3j1C9fGbqhtyTNXG3tzT/nNmIXRI X3pEax10xF4Jm9pKlOm8l3YkfPP5v0/2hDOf8gNcfjldCGoDejdTL4RyEyq4pIlKmn7ezi0Z yBjFwysllgTYKe0w6kUfoEgD7YlLSoV72C6M8SGmx8ULpZyf+qZxpiSCbH4btaxh14byRR4o zyOWoJv72b6zHbFukZnJ39O1/mEYaXoK4wvR9+vZrl/oncdDWEfY5rRgCZRKKHKyRqp40ZQv WPcrLO2s49R2zbmQidzHWjnQoQvuMgCFpWcGSGC5PpdpYpIUgy6Hg7S+cKO7nUi7ROuNGetm OiPIIoyJkKzgW3MYIgC0pCbqDSxqOK0KrdWsX8GEE6GNQs9eYJk4mE+mjyPfdZ/VTnGZ1nMA wZFivf9SJLevPoJK/7vvNYQY0Moce4JkiTYt4IaYu7A1SmUvZtOElBA1ON+GSENYek7TTsUb AEb919v7d+dHcNowOfB/tuxYZX98EQzzKCxvGS/ioAoaBN7PRhXLqjYUJOC3PIHo2i0rHaB0 SgHPnPc6e1hMy70RlSMSY=
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Openpgp: preference=signencrypt
On 18/03/2019 13:20, Jan Beulich wrote:
> >>> On 18.03.19 at 12:27, <andrew.cooper3@xxxxxxxxxx> wrote:
>> * Some of the single-byte versions specify "=q" as the output. This is a
>> remnent of the 32bit build and can be relaxed to "=r" in 64bit builds.
> I have to admit that I don't understand the "relaxed" part of this:
> "q" and "r" represent the exact same set of registers on 64-bit.
> Unless the conversion allows further code folding, I think it wouldn't
> be a bad idea to retain the distinction, just for cases like code
> eventually getting shared via something like lib/x86/.
The change from =q to =r is specifically to allow the folding to +r
>
>> The reason the volatile cast in __cmpxchg_user() can't be dropped is because
>> without it, the compiler uses a stack copy rather than the in-memory copy,
>> which ends up tripping:
>>
>> /* Allowed to change in Accessed/Dirty flags only. */
>> BUG_ON((t ^ old) & ~(intpte_t)(_PAGE_ACCESSED|_PAGE_DIRTY));
> Isn't this hinting at some other shortcoming or even flaw then?
> If the compiler generally did such transformations, I'm afraid a
> lot of other code would be at risk too, including some of what
> you modify here.
I don't think there is any flaw or shortcoming. Without the volatile,
the compiler doesn't know that there are any side effects, so can
legitimately operate on a local stack copy so long as it copies things
back later.
In practice, this is an operation on shared memory which has to happen
on the shared memory pointer.
> In any event I think it would be a good idea to have a code
> comment for this as well.
I don't see how that would help. The same applies to all atomic
operations, even test_bit().
>
>> @@ -40,28 +37,24 @@ static always_inline unsigned long __xchg(
>> switch ( size )
>> {
>> case 1:
>> - asm volatile ( "xchgb %b0,%1"
>> - : "=q" (x)
>> - : "m" (*__xg(ptr)), "0" (x)
>> - : "memory" );
>> + asm volatile ( "xchg %b[x], %[ptr]"
>> + : [x] "+r" (x), [ptr] "+m" (*(uint8_t *)ptr)
>> + :: "memory" );
>> break;
>> case 2:
>> - asm volatile ( "xchgw %w0,%1"
>> - : "=r" (x)
>> - : "m" (*__xg(ptr)), "0" (x)
>> - : "memory" );
>> + asm volatile ( "xchg %w[x], %[ptr]"
>> + : [x] "+r" (x), [ptr] "+m" (*(uint16_t *)ptr)
>> + :: "memory" );
>> break;
>> case 4:
>> - asm volatile ( "xchgl %k0,%1"
>> - : "=r" (x)
>> - : "m" (*__xg(ptr)), "0" (x)
>> - : "memory" );
>> + asm volatile ( "xchg %k[x], %[ptr]"
>> + : [x] "+r" (x), [ptr] "+m" (*(uint32_t *)ptr)
>> + :: "memory" );
>> break;
>> case 8:
>> - asm volatile ( "xchgq %0,%1"
>> - : "=r" (x)
>> - : "m" (*__xg(ptr)), "0" (x)
>> - : "memory" );
>> + asm volatile ( "xchg %q[x], %[ptr]"
>> + : [x] "+r" (x), [ptr] "+m" (*(uint64_t *)ptr)
>> + :: "memory" );
>> break;
> Is the q modifier really useful to have here (and elsewhere below)?
Yes - it is strictly necessary, because otherwise it gets derived from
the type of (x) which is unsigned long even in the smaller size constructs.
>
>> @@ -63,36 +65,38 @@ static always_inline __uint128_t cmpxchg16b_local_(
>> * If no fault occurs then _o is updated to the value we saw at _p. If this
>> * is the same as the initial value of _o then _n is written to location _p.
>> */
>> -#define __cmpxchg_user(_p,_o,_n,_isuff,_oppre,_regtype) \
>> +#define __cmpxchg_user(_p, _o, _n, _oppre) \
>> stac(); \
>> asm volatile ( \
>> - "1: lock; cmpxchg"_isuff" %"_oppre"2,%3\n" \
>> + "1: lock cmpxchg %"_oppre"[new], %[ptr]\n" \
>> "2:\n" \
>> ".section .fixup,\"ax\"\n" \
>> - "3: movl $1,%1\n" \
>> + "3: movl $1, %[rc]\n" \
>> " jmp 2b\n" \
>> ".previous\n" \
>> _ASM_EXTABLE(1b, 3b) \
>> - : "=a" (_o), "=r" (_rc) \
>> - : _regtype (_n), "m" (*__xg((volatile void *)_p)), "0" (_o), "1"
>> (0) \
>> + : "+a" (_o), [rc] "=r" (_rc), \
>> + [ptr] "+m" (*(volatile typeof(*(_p)) *)(_p)) \
>> + : [new] "r" (_n), "[rc]" (0) \
> Wouldn't it further help readability a little if _rc was initialized to zero
> right when getting declared, eliminating the last input arg here (the
> output then would need to be "+r" of course)?
I can do.
> And since then you
> actually touch all lines containing uses of _rc, it would be a good
> opportunity to also rename the variable to get rid of the leading
> underscore.
I'm not sure that is a sensible move. Its a macro-scope variable from
cmpxchg_user() which still needs disambiguating from potential names of
parameters.
>
> Anyway, with at least the "relaxed" part of the description changed
> (e.g. to "converted") or explained verbally in a reply, with or without
> the other items taken care of
> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
Hopefully my reply is sufficient?
~Andrew
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