Re: [Xen-devel] [PATCH v9 10/11] viridian: add implementation of synthetic timers

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 19.03.19 at 13:47, <Paul.Durrant@xxxxxxxxxx> wrote:
>> From: Jan Beulich [mailto:JBeulich@xxxxxxxx]
>> Sent: 19 March 2019 12:18
>> 
>> So perhaps a set
>> pending bit should result in the RDMSR handling to clear the enabled
>> bit in the returned value for a non-periodic timer?
> 
> I get tied in knots every time I think about this and without waiting for a 
> pending timer to stop when it is disabled I see no way of the race, but I 
> think doing that would be prohibitively slow because windows seems to flip 
> between single-shot and periodic timers on quite a frequent basis.

I'm afraid I don't understand: Why a timer or any other complications.
All I'm thinking about is

    case HV_X64_MSR_STIMER0_CONFIG:
    case HV_X64_MSR_STIMER1_CONFIG:
    case HV_X64_MSR_STIMER2_CONFIG:
    case HV_X64_MSR_STIMER3_CONFIG:
    {
        unsigned int stimerx = (idx - HV_X64_MSR_STIMER0_CONFIG) / 2;
        const struct viridian_stimer *vs =
            &array_access_nospec(vv->stimer, stimerx);

        if ( !(viridian_feature_mask(d) & HVMPV_stimer) )
            return X86EMUL_EXCEPTION;

        *val = vs->config.raw;
        if ( !vs->config.periodic && test_bit(stimerx, vv->stimer_pending) )
            *val &= ~1;
        break;
    }

or a suitable equivalent to avoid the literal 1, plus perhaps a
helpful comment.

Jan



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