Re: [Xen-devel] [PATCH 5/5] x86/msr: Fix handling of MSR_AMD_PATCHLEVEL/MSR_IA32_UCODE_REV

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 04.04.19 at 22:26, <andrew.cooper3@xxxxxxxxxx> wrote:
> --- a/xen/arch/x86/msr.c
> +++ b/xen/arch/x86/msr.c
> @@ -135,6 +135,27 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, 
> uint64_t *val)
>          /* Not offered to guests. */
>          goto gp_fault;
>  
> +    case MSR_AMD_PATCHLEVEL:
> +        BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
> +        /*
> +         * AMD and Intel use the same MSR for the current microcode version.
> +         *
> +         * There is no need to jump through the SDM-provided hoops for Intel.
> +         * A guest might itself perform the "write 0, CPUID, read" sequence,
> +         * but servicing the CPUID for the guest typically wont result in
> +         * actually executing a CPUID instruction.
> +         *
> +         * As a guest can't influence the value of this MSR, the value will 
> be
> +         * from Xen's last microcode load, which can be forwarded straight to
> +         * the guest.
> +         */
> +        if ( !(cp->x86_vendor & (X86_VENDOR_INTEL |X86_VENDOR_AMD)) ||

Nit: There's a missing blank after the | here.

Jan



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