Re: [Xen-devel] [PATCH 4/5] x86/cpu: Create Hygon Dhyana architecture support file

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 05.04.19 at 17:30, <puwen@xxxxxxxx> wrote:
> On 2019/4/5 17:38, Jan Beulich wrote:
>> On 04.04.19 at 22:26, <andrew.cooper3@xxxxxxxxxx> wrote:
>>> +   /*
>>> +    * If the user has explicitly chosen to disable Memory Disambiguation
>>> +    * to mitigiate Speculative Store Bypass, poke the appropriate MSR.
>>> +    */
>>> +   if (opt_ssbd && !rdmsr_safe(MSR_AMD64_LS_CFG, value)) {
>>> +           value |= 1ull << 10;
>>> +           wrmsr_safe(MSR_AMD64_LS_CFG, value);
>>> +   }
>> 
>> Like the above, this lacks a model check. Is it really expected for
>> all future Hygon models to supports both in exactly the same
> 
> For current Hygon family 18h, all models will have the same meaning.

Oh, I'm sorry - I meant "families", not "models" in my earlier reply
(throughout). I'm frequently mixing this up when switching between
"Intel" and "AMD" modes, unfortunately.

Jan



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