[Xen-devel] [PATCH 0/3] x86: Fix boot time detection of SMT settings

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

It turns out that on Intel hardware, CPUID.0xb.smt_shift represents the
hardware capability, not the current configuration.  Therefore, the L1TF
nagging warning triggers even when the admin has disabled hyperthreading in
the firmware.

The way to fix this is using the MSR_INTEL_CORE_THREAD_COUNT.  Several updates
to the Intel MSR documentation are expected to be forthcoming.

See individual patches for details.

Andrew Cooper (3):
  x86/spec-ctrl: Reposition the XPTI command line parsing logic
  x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNT
  x86/boot: Detect the firmware SMT setting correctly on Intel hardware

 xen/arch/x86/cpu/amd.c          |   2 +-
 xen/arch/x86/msr.c              |   2 +
 xen/arch/x86/spec_ctrl.c        | 182 ++++++++++++++++++++++++----------------
 xen/include/asm-x86/msr-index.h |   4 +
 4 files changed, 119 insertions(+), 71 deletions(-)

-- 
2.1.4


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