Re: [Xen-devel] [PATCH 1/6] xen: extend XEN_DOMCTL_memory_mapping to handle cacheability

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 26.04.19 at 00:31, <sstabellini@xxxxxxxxxx> wrote:
> On Thu, 25 Apr 2019, Jan Beulich wrote:
>> But I agree with Julien (in case this wasn't explicit enough from
>> my earlier replay) that it first needs to be clarified whether such
>> an interface is wanted in the first place.
> 
> I have written down a few more details about the use-case elsewhere,
> I'll copy/paste here:
> 
>   Xilinx MPSoC has two Cortex R5 cpus in addition to four Cortex A53 cpus
>   on the board.  It is also possible to add additional Cortex M4 cpus and
>   Microblaze cpus in fabric. There could be dozen independent processors.
>   Users need to exchange data between the heterogeneous cpus. They usually
>   set up their own ring structures over shared memory, or they use
>   OpenAMP.  Either way, they need to share a cacheable memory region
>   between them.  The MPSoC is very flexible and the memory region can come
>   from a multitude of sources, including a portion of normal memory, or a
>   portion of a special memory area on the board. There are a couple of
>   special SRAM banks 64K or 256K large that could be used for that. Also,
>   PRAM can be easily added in fabric and used for the purpose.
> 
> At the very least to handle the special memory regions, we need to be
> able to allow iomem to map them as cacheable memory to a DomU. So I do
> think we need this interface extension.
> 
> Let me know if you still have any doubts/questions. Otherwise I'll work
> toward respinning the series in the proposed direction.

Well, as long as Julien and you agree that such an interface is
needed on Arm, this is fine with me.

Jan



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