|
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 2/2] x86emul: support CPUID subleaves for vcpu_has_*()
The AVX512_BF16 feature flag resides in leaf 7 sub-leaf 1. Expand
infrastructure accordingly before enabling support for those insns.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1845,6 +1845,7 @@ in_protmode(
static bool vcpu_has(
unsigned int eax,
+ unsigned int ecx,
unsigned int reg,
unsigned int bit,
struct x86_emulate_ctxt *ctxt,
@@ -1854,7 +1855,7 @@ static bool vcpu_has(
int rc = X86EMUL_OKAY;
fail_if(!ops->cpuid);
- rc = ops->cpuid(eax, 0, &res, ctxt);
+ rc = ops->cpuid(eax, ecx, &res, ctxt);
if ( rc == X86EMUL_OKAY )
{
switch ( reg )
@@ -1873,76 +1874,78 @@ static bool vcpu_has(
return rc == X86EMUL_OKAY;
}
-#define vcpu_has_fpu() vcpu_has( 1, EDX, 0, ctxt, ops)
-#define vcpu_has_sep() vcpu_has( 1, EDX, 11, ctxt, ops)
-#define vcpu_has_cx8() vcpu_has( 1, EDX, 8, ctxt, ops)
-#define vcpu_has_cmov() vcpu_has( 1, EDX, 15, ctxt, ops)
-#define vcpu_has_clflush() vcpu_has( 1, EDX, 19, ctxt, ops)
-#define vcpu_has_mmx() vcpu_has( 1, EDX, 23, ctxt, ops)
-#define vcpu_has_sse() vcpu_has( 1, EDX, 25, ctxt, ops)
-#define vcpu_has_sse2() vcpu_has( 1, EDX, 26, ctxt, ops)
-#define vcpu_has_sse3() vcpu_has( 1, ECX, 0, ctxt, ops)
-#define vcpu_has_pclmulqdq() vcpu_has( 1, ECX, 1, ctxt, ops)
-#define vcpu_has_ssse3() vcpu_has( 1, ECX, 9, ctxt, ops)
-#define vcpu_has_fma() vcpu_has( 1, ECX, 12, ctxt, ops)
-#define vcpu_has_cx16() vcpu_has( 1, ECX, 13, ctxt, ops)
-#define vcpu_has_sse4_1() vcpu_has( 1, ECX, 19, ctxt, ops)
-#define vcpu_has_sse4_2() vcpu_has( 1, ECX, 20, ctxt, ops)
-#define vcpu_has_movbe() vcpu_has( 1, ECX, 22, ctxt, ops)
-#define vcpu_has_popcnt() vcpu_has( 1, ECX, 23, ctxt, ops)
-#define vcpu_has_aesni() vcpu_has( 1, ECX, 25, ctxt, ops)
-#define vcpu_has_avx() vcpu_has( 1, ECX, 28, ctxt, ops)
-#define vcpu_has_f16c() vcpu_has( 1, ECX, 29, ctxt, ops)
-#define vcpu_has_rdrand() vcpu_has( 1, ECX, 30, ctxt, ops)
-#define vcpu_has_mmxext() (vcpu_has(0x80000001, EDX, 22, ctxt, ops) || \
+#define NA 0
+
+#define vcpu_has_fpu() vcpu_has( 1, NA, EDX, 0, ctxt, ops)
+#define vcpu_has_sep() vcpu_has( 1, NA, EDX, 11, ctxt, ops)
+#define vcpu_has_cx8() vcpu_has( 1, NA, EDX, 8, ctxt, ops)
+#define vcpu_has_cmov() vcpu_has( 1, NA, EDX, 15, ctxt, ops)
+#define vcpu_has_clflush() vcpu_has( 1, NA, EDX, 19, ctxt, ops)
+#define vcpu_has_mmx() vcpu_has( 1, NA, EDX, 23, ctxt, ops)
+#define vcpu_has_sse() vcpu_has( 1, NA, EDX, 25, ctxt, ops)
+#define vcpu_has_sse2() vcpu_has( 1, NA, EDX, 26, ctxt, ops)
+#define vcpu_has_sse3() vcpu_has( 1, NA, ECX, 0, ctxt, ops)
+#define vcpu_has_pclmulqdq() vcpu_has( 1, NA, ECX, 1, ctxt, ops)
+#define vcpu_has_ssse3() vcpu_has( 1, NA, ECX, 9, ctxt, ops)
+#define vcpu_has_fma() vcpu_has( 1, NA, ECX, 12, ctxt, ops)
+#define vcpu_has_cx16() vcpu_has( 1, NA, ECX, 13, ctxt, ops)
+#define vcpu_has_sse4_1() vcpu_has( 1, NA, ECX, 19, ctxt, ops)
+#define vcpu_has_sse4_2() vcpu_has( 1, NA, ECX, 20, ctxt, ops)
+#define vcpu_has_movbe() vcpu_has( 1, NA, ECX, 22, ctxt, ops)
+#define vcpu_has_popcnt() vcpu_has( 1, NA, ECX, 23, ctxt, ops)
+#define vcpu_has_aesni() vcpu_has( 1, NA, ECX, 25, ctxt, ops)
+#define vcpu_has_avx() vcpu_has( 1, NA, ECX, 28, ctxt, ops)
+#define vcpu_has_f16c() vcpu_has( 1, NA, ECX, 29, ctxt, ops)
+#define vcpu_has_rdrand() vcpu_has( 1, NA, ECX, 30, ctxt, ops)
+#define vcpu_has_mmxext() (vcpu_has(0x80000001, NA, EDX, 22, ctxt, ops) ||
\
vcpu_has_sse())
-#define vcpu_has_3dnow_ext() vcpu_has(0x80000001, EDX, 30, ctxt, ops)
-#define vcpu_has_3dnow() vcpu_has(0x80000001, EDX, 31, ctxt, ops)
-#define vcpu_has_lahf_lm() vcpu_has(0x80000001, ECX, 0, ctxt, ops)
-#define vcpu_has_cr8_legacy() vcpu_has(0x80000001, ECX, 4, ctxt, ops)
-#define vcpu_has_lzcnt() vcpu_has(0x80000001, ECX, 5, ctxt, ops)
-#define vcpu_has_sse4a() vcpu_has(0x80000001, ECX, 6, ctxt, ops)
-#define vcpu_has_misalignsse() vcpu_has(0x80000001, ECX, 7, ctxt, ops)
-#define vcpu_has_xop() vcpu_has(0x80000001, ECX, 12, ctxt, ops)
-#define vcpu_has_fma4() vcpu_has(0x80000001, ECX, 16, ctxt, ops)
-#define vcpu_has_tbm() vcpu_has(0x80000001, ECX, 21, ctxt, ops)
-#define vcpu_has_monitorx() vcpu_has(0x80000001, ECX, 29, ctxt, ops)
-#define vcpu_has_bmi1() vcpu_has( 7, EBX, 3, ctxt, ops)
-#define vcpu_has_hle() vcpu_has( 7, EBX, 4, ctxt, ops)
-#define vcpu_has_avx2() vcpu_has( 7, EBX, 5, ctxt, ops)
-#define vcpu_has_bmi2() vcpu_has( 7, EBX, 8, ctxt, ops)
-#define vcpu_has_invpcid() vcpu_has( 7, EBX, 10, ctxt, ops)
-#define vcpu_has_rtm() vcpu_has( 7, EBX, 11, ctxt, ops)
-#define vcpu_has_mpx() vcpu_has( 7, EBX, 14, ctxt, ops)
-#define vcpu_has_avx512f() vcpu_has( 7, EBX, 16, ctxt, ops)
-#define vcpu_has_avx512dq() vcpu_has( 7, EBX, 17, ctxt, ops)
-#define vcpu_has_rdseed() vcpu_has( 7, EBX, 18, ctxt, ops)
-#define vcpu_has_adx() vcpu_has( 7, EBX, 19, ctxt, ops)
-#define vcpu_has_smap() vcpu_has( 7, EBX, 20, ctxt, ops)
-#define vcpu_has_avx512_ifma() vcpu_has( 7, EBX, 21, ctxt, ops)
-#define vcpu_has_clflushopt() vcpu_has( 7, EBX, 23, ctxt, ops)
-#define vcpu_has_clwb() vcpu_has( 7, EBX, 24, ctxt, ops)
-#define vcpu_has_avx512pf() vcpu_has( 7, EBX, 26, ctxt, ops)
-#define vcpu_has_avx512er() vcpu_has( 7, EBX, 27, ctxt, ops)
-#define vcpu_has_avx512cd() vcpu_has( 7, EBX, 28, ctxt, ops)
-#define vcpu_has_sha() vcpu_has( 7, EBX, 29, ctxt, ops)
-#define vcpu_has_avx512bw() vcpu_has( 7, EBX, 30, ctxt, ops)
-#define vcpu_has_avx512vl() vcpu_has( 7, EBX, 31, ctxt, ops)
-#define vcpu_has_avx512_vbmi() vcpu_has( 7, ECX, 1, ctxt, ops)
-#define vcpu_has_avx512_vbmi2() vcpu_has( 7, ECX, 6, ctxt, ops)
-#define vcpu_has_gfni() vcpu_has( 7, ECX, 8, ctxt, ops)
-#define vcpu_has_vaes() vcpu_has( 7, ECX, 9, ctxt, ops)
-#define vcpu_has_vpclmulqdq() vcpu_has( 7, ECX, 10, ctxt, ops)
-#define vcpu_has_avx512_vnni() vcpu_has( 7, ECX, 11, ctxt, ops)
-#define vcpu_has_avx512_bitalg() vcpu_has( 7, ECX, 12, ctxt, ops)
-#define vcpu_has_avx512_vpopcntdq() vcpu_has( 7, ECX, 14, ctxt, ops)
-#define vcpu_has_rdpid() vcpu_has( 7, ECX, 22, ctxt, ops)
-#define vcpu_has_movdiri() vcpu_has( 7, ECX, 27, ctxt, ops)
-#define vcpu_has_movdir64b() vcpu_has( 7, ECX, 28, ctxt, ops)
-#define vcpu_has_avx512_4vnniw() vcpu_has( 7, EDX, 2, ctxt, ops)
-#define vcpu_has_avx512_4fmaps() vcpu_has( 7, EDX, 3, ctxt, ops)
-#define vcpu_has_clzero() vcpu_has(0x80000008, EBX, 0, ctxt, ops)
-#define vcpu_has_wbnoinvd() vcpu_has(0x80000008, EBX, 9, ctxt, ops)
+#define vcpu_has_3dnow_ext() vcpu_has(0x80000001, NA, EDX, 30, ctxt, ops)
+#define vcpu_has_3dnow() vcpu_has(0x80000001, NA, EDX, 31, ctxt, ops)
+#define vcpu_has_lahf_lm() vcpu_has(0x80000001, NA, ECX, 0, ctxt, ops)
+#define vcpu_has_cr8_legacy() vcpu_has(0x80000001, NA, ECX, 4, ctxt, ops)
+#define vcpu_has_lzcnt() vcpu_has(0x80000001, NA, ECX, 5, ctxt, ops)
+#define vcpu_has_sse4a() vcpu_has(0x80000001, NA, ECX, 6, ctxt, ops)
+#define vcpu_has_misalignsse() vcpu_has(0x80000001, NA, ECX, 7, ctxt, ops)
+#define vcpu_has_xop() vcpu_has(0x80000001, NA, ECX, 12, ctxt, ops)
+#define vcpu_has_fma4() vcpu_has(0x80000001, NA, ECX, 16, ctxt, ops)
+#define vcpu_has_tbm() vcpu_has(0x80000001, NA, ECX, 21, ctxt, ops)
+#define vcpu_has_monitorx() vcpu_has(0x80000001, NA, ECX, 29, ctxt, ops)
+#define vcpu_has_bmi1() vcpu_has( 7, 0, EBX, 3, ctxt, ops)
+#define vcpu_has_hle() vcpu_has( 7, 0, EBX, 4, ctxt, ops)
+#define vcpu_has_avx2() vcpu_has( 7, 0, EBX, 5, ctxt, ops)
+#define vcpu_has_bmi2() vcpu_has( 7, 0, EBX, 8, ctxt, ops)
+#define vcpu_has_invpcid() vcpu_has( 7, 0, EBX, 10, ctxt, ops)
+#define vcpu_has_rtm() vcpu_has( 7, 0, EBX, 11, ctxt, ops)
+#define vcpu_has_mpx() vcpu_has( 7, 0, EBX, 14, ctxt, ops)
+#define vcpu_has_avx512f() vcpu_has( 7, 0, EBX, 16, ctxt, ops)
+#define vcpu_has_avx512dq() vcpu_has( 7, 0, EBX, 17, ctxt, ops)
+#define vcpu_has_rdseed() vcpu_has( 7, 0, EBX, 18, ctxt, ops)
+#define vcpu_has_adx() vcpu_has( 7, 0, EBX, 19, ctxt, ops)
+#define vcpu_has_smap() vcpu_has( 7, 0, EBX, 20, ctxt, ops)
+#define vcpu_has_avx512_ifma() vcpu_has( 7, 0, EBX, 21, ctxt, ops)
+#define vcpu_has_clflushopt() vcpu_has( 7, 0, EBX, 23, ctxt, ops)
+#define vcpu_has_clwb() vcpu_has( 7, 0, EBX, 24, ctxt, ops)
+#define vcpu_has_avx512pf() vcpu_has( 7, 0, EBX, 26, ctxt, ops)
+#define vcpu_has_avx512er() vcpu_has( 7, 0, EBX, 27, ctxt, ops)
+#define vcpu_has_avx512cd() vcpu_has( 7, 0, EBX, 28, ctxt, ops)
+#define vcpu_has_sha() vcpu_has( 7, 0, EBX, 29, ctxt, ops)
+#define vcpu_has_avx512bw() vcpu_has( 7, 0, EBX, 30, ctxt, ops)
+#define vcpu_has_avx512vl() vcpu_has( 7, 0, EBX, 31, ctxt, ops)
+#define vcpu_has_avx512_vbmi() vcpu_has( 7, 0, ECX, 1, ctxt, ops)
+#define vcpu_has_avx512_vbmi2() vcpu_has( 7, 0, ECX, 6, ctxt, ops)
+#define vcpu_has_gfni() vcpu_has( 7, 0, ECX, 8, ctxt, ops)
+#define vcpu_has_vaes() vcpu_has( 7, 0, ECX, 9, ctxt, ops)
+#define vcpu_has_vpclmulqdq() vcpu_has( 7, 0, ECX, 10, ctxt, ops)
+#define vcpu_has_avx512_vnni() vcpu_has( 7, 0, ECX, 11, ctxt, ops)
+#define vcpu_has_avx512_bitalg() vcpu_has( 7, 0, ECX, 12, ctxt, ops)
+#define vcpu_has_avx512_vpopcntdq() vcpu_has( 7, 0, ECX, 14, ctxt, ops)
+#define vcpu_has_rdpid() vcpu_has( 7, 0, ECX, 22, ctxt, ops)
+#define vcpu_has_movdiri() vcpu_has( 7, 0, ECX, 27, ctxt, ops)
+#define vcpu_has_movdir64b() vcpu_has( 7, 0, ECX, 28, ctxt, ops)
+#define vcpu_has_avx512_4vnniw() vcpu_has( 7, 0, EDX, 2, ctxt, ops)
+#define vcpu_has_avx512_4fmaps() vcpu_has( 7, 0, EDX, 3, ctxt, ops)
+#define vcpu_has_clzero() vcpu_has(0x80000008, NA, EBX, 0, ctxt, ops)
+#define vcpu_has_wbnoinvd() vcpu_has(0x80000008, NA, EBX, 9, ctxt, ops)
#define vcpu_must_have(feat) \
generate_exception_if(!vcpu_has_##feat(), EXC_UD)
_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel
|
 |
Lists.xenproject.org is hosted with RackSpace, monitoring our |