Re: [Xen-devel] [PATCH MM-PART1 v3 1/8] xen/arm: Don't boot Xen on platform using AIVIVT instruction caches

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Tue, 14 May 2019, Julien Grall wrote:
> The AIVIVT is a type of instruction cache available on Armv7. This is
> the only cache not implementing the IVIPT extension and therefore
> requiring specific care.
> 
> To simplify maintenance requirements, Xen will not boot on platform
> using AIVIVT cache.
> 
> This should not be an issue because Xen Arm32 can only boot on a small
> number of processors (see arch/arm/arm32/proc-v7.S). All of them are
> not using AIVIVT cache.
> 
> Signed-off-by: Julien Grall <julien.grall@xxxxxxx>

As we have already discussed, I am OK with this and neither of us
foresee any issues. Given that it could be considered as a drop in
support for something, I think it would be nice to send an email outside
of the series to say we won't support AIVIVT processors any longer,
using words easier to understand to users (not necessarily developers).
Would you be able to do that? I can help you with the text.


> ---
> 
>     Changes in v3:
>         - Patch added
> ---
>  xen/arch/arm/setup.c            | 5 +++++
>  xen/include/asm-arm/processor.h | 5 +++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> index ccb0f181ea..faaf029b99 100644
> --- a/xen/arch/arm/setup.c
> +++ b/xen/arch/arm/setup.c
> @@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, 
> size_t dtb_size)
>      unsigned long boot_mfn_start, boot_mfn_end;
>      int i;
>      void *fdt;
> +    const uint32_t ctr = READ_CP32(CTR);
>  
>      if ( !bootinfo.mem.nr_banks )
>          panic("No memory bank\n");
>  
> +    /* We only supports instruction caches implementing the IVIPT extension. 
> */

Please mention that IVIPT can only be implemented by PIPT and VIPT
caches, not by AIVIVT caches. That should make it straightforward to
understand the reason for the panic below.


> +    if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) == CTR_L1Ip_AIVIVT )
> +        panic("AIVIVT instruction cache not supported\n");
> +
>      init_pdx();
>  
>      ram_start = bootinfo.mem.bank[0].start;
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index b5f515805d..04b05b3f39 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -6,6 +6,11 @@
>  #endif
>  #include <public/arch-arm.h>
>  
> +/* CTR Cache Type Register */
> +#define CTR_L1Ip_MASK       0x3
> +#define CTR_L1Ip_SHIFT      14
> +#define CTR_L1Ip_AIVIVT     0x1
> +
>  /* MIDR Main ID Register */
>  #define MIDR_REVISION_MASK      0xf
>  #define MIDR_RESIVION(midr)     ((midr) & MIDR_REVISION_MASK)
> -- 
> 2.11.0
> 

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