Re: [Xen-devel] [PATCH MM-PART2 RESEND v2 14/19] xen/arm32: mm: Avoid cleaning the cache for secondary CPUs page-tables

[Julien Grall <julien.grall@xxxxxxx>]

Hi,

On 05/06/2019 11:19, Julien Grall wrote:
> On 05/06/2019 00:11, Stefano Stabellini wrote:
> > On Tue, 14 May 2019, Julien Grall wrote:
> > > The page-table walker is configured to use the same shareability and
> > > cacheability as the access performed when updating the page-tables. This
> > > means cleaning the cache for secondary CPUs runtime page-tables is
> > > unnecessary.
> > All right. Is there an explicit configuration for the shareability and
> > cacheability used by the page-table walker or is it specified as such in
> > the Arm Arm?
> See the configuration of TCR_EL2, I can mention it.
>
> > Also, isn't it possible that CPUs on a different cluster
> > (big.LITTLE) would have issues with this if the cache could be split
> > between the two clusters?
Gentle ping, can you please clarify your question.

> I don't understand this... Cache should be coherent when a CPU leaves EL3.
> But we already share some bits of the page tables between the processor (see 
> create_xen_page_tables). So I don't see where there is a possible problem here.
Cheers,

--
Julien Grall

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