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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [xen-unstable test] 138769: regressions - FAIL
flight 138769 xen-unstable real [real] http://logs.test-lab.xenproject.org/osstest/logs/138769/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-amd64-xl-qemuu-ovmf-amd64 7 xen-boot fail REGR. vs. 138745 test-amd64-i386-xl-raw 10 debian-di-install fail REGR. vs. 138745 Tests which did not succeed, but are not blocking: test-arm64-arm64-examine 11 examine-serial/bootloader fail like 138717 test-amd64-amd64-xl-qemut-win7-amd64 17 guest-stop fail like 138745 test-amd64-amd64-xl-qemuu-win7-amd64 17 guest-stop fail like 138745 test-armhf-armhf-libvirt 14 saverestore-support-check fail like 138745 test-amd64-amd64-xl-qemuu-ws16-amd64 17 guest-stop fail like 138745 test-amd64-i386-xl-qemut-win7-amd64 17 guest-stop fail like 138745 test-armhf-armhf-libvirt-raw 13 saverestore-support-check fail like 138745 test-amd64-amd64-xl-qemut-ws16-amd64 17 guest-stop fail like 138745 test-amd64-i386-xl-qemuu-win7-amd64 17 guest-stop fail like 138745 test-amd64-i386-xl-qemuu-ws16-amd64 17 guest-stop fail like 138745 test-amd64-i386-libvirt 13 migrate-support-check fail never pass test-amd64-amd64-libvirt 13 migrate-support-check fail never pass test-amd64-i386-libvirt-xsm 13 migrate-support-check fail never pass test-arm64-arm64-xl-seattle 13 migrate-support-check fail never pass test-arm64-arm64-xl-seattle 14 saverestore-support-check fail never pass test-amd64-amd64-libvirt-xsm 13 migrate-support-check fail never pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 11 migrate-support-check fail never pass test-amd64-amd64-qemuu-nested-amd 17 debian-hvm-install/l1/l2 fail never pass test-arm64-arm64-xl-xsm 13 migrate-support-check fail never pass test-arm64-arm64-xl-xsm 14 saverestore-support-check fail never pass test-arm64-arm64-libvirt-xsm 13 migrate-support-check fail never pass test-arm64-arm64-libvirt-xsm 14 saverestore-support-check fail never pass test-arm64-arm64-xl-credit2 13 migrate-support-check fail never pass test-arm64-arm64-xl-credit2 14 saverestore-support-check fail never pass test-arm64-arm64-xl 13 migrate-support-check fail never pass test-arm64-arm64-xl 14 saverestore-support-check fail never pass test-arm64-arm64-xl-credit1 13 migrate-support-check fail never pass test-arm64-arm64-xl-credit1 14 saverestore-support-check fail never pass test-arm64-arm64-xl-thunderx 13 migrate-support-check fail never pass test-arm64-arm64-xl-thunderx 14 saverestore-support-check fail never pass test-armhf-armhf-xl-arndale 13 migrate-support-check fail never pass test-armhf-armhf-xl-arndale 14 saverestore-support-check fail never pass test-amd64-amd64-libvirt-vhd 12 migrate-support-check fail never pass test-armhf-armhf-libvirt 13 migrate-support-check fail never pass test-armhf-armhf-xl-credit1 13 migrate-support-check fail never pass test-armhf-armhf-xl-credit1 14 saverestore-support-check fail never pass test-armhf-armhf-xl 13 migrate-support-check fail never pass test-armhf-armhf-xl 14 saverestore-support-check fail never pass test-armhf-armhf-xl-multivcpu 13 migrate-support-check fail never pass test-armhf-armhf-xl-multivcpu 14 saverestore-support-check fail never pass test-armhf-armhf-xl-rtds 13 migrate-support-check fail never pass test-armhf-armhf-xl-rtds 14 saverestore-support-check fail never pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm 11 migrate-support-check fail never pass test-amd64-i386-xl-pvshim 12 guest-start fail never pass test-armhf-armhf-xl-cubietruck 13 migrate-support-check fail never pass test-armhf-armhf-xl-cubietruck 14 saverestore-support-check fail never pass test-armhf-armhf-libvirt-raw 12 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 12 migrate-support-check fail never pass test-armhf-armhf-xl-vhd 13 saverestore-support-check fail never pass test-armhf-armhf-xl-credit2 13 migrate-support-check fail never pass test-armhf-armhf-xl-credit2 14 saverestore-support-check fail never pass test-amd64-amd64-xl-qemuu-win10-i386 10 windows-install fail never pass test-amd64-i386-xl-qemuu-win10-i386 10 windows-install fail never pass test-amd64-amd64-xl-qemut-win10-i386 10 windows-install fail never pass test-amd64-i386-xl-qemut-win10-i386 10 windows-install fail never pass test-amd64-i386-xl-qemut-ws16-amd64 17 guest-stop fail never pass version targeted for testing: xen 843cec0de800a5f925f8071a7f58f3fb1c6b6eb6 baseline version: xen 93ef224d63f9f04a0897d64981c619eb4816c0d3 Last test of basis 138745 2019-07-04 04:12:24 Z 3 days Testing same since 138769 2019-07-05 17:01:01 Z 1 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> Anthony PERARD <anthony.perard@xxxxxxxxxx> Ian Jackson <ian.jackson@xxxxxxxxxxxxx> Jan Beulich <jbeulich@xxxxxxxx> Juergen Gross <jgross@xxxxxxxx> Paul Durrant <paul.durrant@xxxxxxxxxx> Stefano Stabellini <sstabellini@xxxxxxxxxx> Wei Liu <wl@xxxxxxx> jobs: build-amd64-xsm pass build-arm64-xsm pass build-i386-xsm pass build-amd64-xtf pass build-amd64 pass build-arm64 pass build-armhf pass build-i386 pass build-amd64-libvirt pass build-arm64-libvirt pass build-armhf-libvirt pass build-i386-libvirt pass build-amd64-prev pass build-i386-prev pass build-amd64-pvops pass build-arm64-pvops pass build-armhf-pvops pass build-i386-pvops pass test-xtf-amd64-amd64-1 pass test-xtf-amd64-amd64-2 pass test-xtf-amd64-amd64-3 pass test-xtf-amd64-amd64-4 pass test-xtf-amd64-amd64-5 pass test-amd64-amd64-xl pass test-arm64-arm64-xl pass test-armhf-armhf-xl pass test-amd64-i386-xl pass test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm pass test-amd64-i386-libvirt-qemuu-debianhvm-amd64-xsm pass test-amd64-amd64-xl-qemut-stubdom-debianhvm-amd64-xsm pass test-amd64-i386-xl-qemut-stubdom-debianhvm-amd64-xsm pass test-amd64-amd64-xl-qemut-debianhvm-i386-xsm pass test-amd64-i386-xl-qemut-debianhvm-i386-xsm pass test-amd64-amd64-xl-qemuu-debianhvm-i386-xsm pass test-amd64-i386-xl-qemuu-debianhvm-i386-xsm pass test-amd64-amd64-libvirt-xsm pass test-arm64-arm64-libvirt-xsm pass test-amd64-i386-libvirt-xsm pass test-amd64-amd64-xl-xsm pass test-arm64-arm64-xl-xsm pass test-amd64-i386-xl-xsm pass test-amd64-amd64-qemuu-nested-amd fail test-amd64-amd64-xl-pvhv2-amd pass test-amd64-i386-qemut-rhel6hvm-amd pass test-amd64-i386-qemuu-rhel6hvm-amd pass test-amd64-amd64-xl-qemut-debianhvm-amd64 pass test-amd64-i386-xl-qemut-debianhvm-amd64 pass test-amd64-amd64-xl-qemuu-debianhvm-amd64 pass test-amd64-i386-xl-qemuu-debianhvm-amd64 pass test-amd64-i386-freebsd10-amd64 pass test-amd64-amd64-xl-qemuu-ovmf-amd64 fail test-amd64-i386-xl-qemuu-ovmf-amd64 pass test-amd64-amd64-xl-qemut-win7-amd64 fail test-amd64-i386-xl-qemut-win7-amd64 fail test-amd64-amd64-xl-qemuu-win7-amd64 fail test-amd64-i386-xl-qemuu-win7-amd64 fail test-amd64-amd64-xl-qemut-ws16-amd64 fail test-amd64-i386-xl-qemut-ws16-amd64 fail test-amd64-amd64-xl-qemuu-ws16-amd64 fail test-amd64-i386-xl-qemuu-ws16-amd64 fail test-armhf-armhf-xl-arndale pass test-amd64-amd64-xl-credit1 pass test-arm64-arm64-xl-credit1 pass test-armhf-armhf-xl-credit1 pass test-amd64-amd64-xl-credit2 pass test-arm64-arm64-xl-credit2 pass test-armhf-armhf-xl-credit2 pass test-armhf-armhf-xl-cubietruck pass test-amd64-amd64-xl-qemuu-dmrestrict-amd64-dmrestrict pass test-amd64-i386-xl-qemuu-dmrestrict-amd64-dmrestrict pass test-amd64-amd64-examine pass test-arm64-arm64-examine pass test-armhf-armhf-examine pass test-amd64-i386-examine pass test-amd64-i386-freebsd10-i386 pass test-amd64-amd64-xl-qemut-win10-i386 fail test-amd64-i386-xl-qemut-win10-i386 fail test-amd64-amd64-xl-qemuu-win10-i386 fail test-amd64-i386-xl-qemuu-win10-i386 fail test-amd64-amd64-qemuu-nested-intel pass test-amd64-amd64-xl-pvhv2-intel pass test-amd64-i386-qemut-rhel6hvm-intel pass test-amd64-i386-qemuu-rhel6hvm-intel pass test-amd64-amd64-libvirt pass test-armhf-armhf-libvirt pass test-amd64-i386-libvirt pass test-amd64-amd64-livepatch pass test-amd64-i386-livepatch pass test-amd64-amd64-migrupgrade pass test-amd64-i386-migrupgrade pass test-amd64-amd64-xl-multivcpu pass test-armhf-armhf-xl-multivcpu pass test-amd64-amd64-pair pass test-amd64-i386-pair pass test-amd64-amd64-libvirt-pair pass test-amd64-i386-libvirt-pair pass test-amd64-amd64-amd64-pvgrub pass test-amd64-amd64-i386-pvgrub pass test-amd64-amd64-xl-pvshim pass test-amd64-i386-xl-pvshim fail test-amd64-amd64-pygrub pass test-amd64-amd64-xl-qcow2 pass test-armhf-armhf-libvirt-raw pass test-amd64-i386-xl-raw fail test-amd64-amd64-xl-rtds pass test-armhf-armhf-xl-rtds pass test-arm64-arm64-xl-seattle pass test-amd64-amd64-xl-qemuu-debianhvm-amd64-shadow pass test-amd64-i386-xl-qemuu-debianhvm-amd64-shadow pass test-amd64-amd64-xl-shadow pass test-amd64-i386-xl-shadow pass test-arm64-arm64-xl-thunderx pass test-amd64-amd64-libvirt-vhd pass test-armhf-armhf-xl-vhd pass ------------------------------------------------------------ sg-report-flight on osstest.test-lab.xenproject.org logs: /home/logs/logs images: /home/logs/images Logs, config files, etc. are available at http://logs.test-lab.xenproject.org/osstest/logs Explanation of these reports, and of osstest in general, is at http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master Test harness code can be found at http://xenbits.xen.org/gitweb?p=osstest.git;a=summary Not pushing. ------------------------------------------------------------ commit 843cec0de800a5f925f8071a7f58f3fb1c6b6eb6 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Fri Jul 5 10:42:36 2019 +0200 x86emul: complete support of AVX512_VBMI insns Also add testing of ones support for which was added before. Sadly gcc's command line option naming is not in line with Intel's naming of the feature, which makes it necessary to mis-name things in the test harness. Since the only new insn here and in particular its memory access pattern follows the usual scheme, I didn't think it was necessary to add a contrived test specifically for it, beyond the Disp8 scaling one. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 37ccca740c2621f8984948a10486d16325e0f175 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Fri Jul 5 10:41:44 2019 +0200 x86emul: support AVX512CD insns Since the insns here and in particular their memory access patterns follow the usual scheme I didn't think it was necessary to add contrived tests specifically for them, beyond the Disp8 scaling ones. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 467e91bde7207f7fc23b6edc9ab9b4d8044c4e36 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Fri Jul 5 10:40:55 2019 +0200 x86emul: support AVX512PF insns Some adjustments are necessary to the EVEX Disp8 scaling test code to account for the zero byte reads/writes, which get issued for the test harness only. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 7d569b848036532f4cdb700ff8b8021c036160c3 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Fri Jul 5 10:40:10 2019 +0200 x86emul: support AVX512F scatter insns This completes support of AVX512F in the insn emulator. Note that in the test harness there's a little bit of trickery needed to get around the not fully consistent naming of AVX512VL gather and scatter compiler built-ins. To suppress expansion of the "di" and "si" tokens they get constructed by token concatenation in BS(), which is different from BG(). Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 062a7faded0a4e3bad789c4e8906cc0fa2400bde Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Fri Jul 5 10:39:41 2019 +0200 x86emul: add high register S/G test cases In order to verify that in particular the index register decoding works correctly in the S/G emulation paths, add dedicated (64-bit only) cases disallowing the compiler to use the lower registers. Other than in the generic SIMD case, where occasional uses of %xmm or %ymm registers in generated code cause various internal compiler errors when disallowing use of all of the lower 16 registers (apparently due to insn templates trying to use AVX2 encodings), doing so here in the AVX512F case looks to be fine. While the main goal here is the AVX512F case, add an AVX2 variant as well. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit c033fe6e7b053b2f0782f4d66715a82505f03569 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Fri Jul 5 10:38:26 2019 +0200 x86emul: support AVX512F gather insns Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 5f55389d696054e97ad0805989bc28b1dcc4ccc7 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 17:43:57 2019 +0200 x86emul: test harness adjustments for AVX512F S/G insns There was an encoding mistake in the EVEX Disp8 test code, which was benign (due to %rdx getting set to zero) to all non-vSIB tests as it mistakenly encoded <disp8>(%rdx,%rdx) instead of <disp8>(%rdx,%riz). In the vSIB case this meant <disp8>(%rdx,%zmm2) instead of the intended <disp8>(%rdx,%zmm4). Likewise the access count check wasn't entirely correct for the S/G case: In the quad-word-index but dword-data case only half the number of full vector elements get accessed. As an unrelated change in the main test harness source file distinguish the "n/a" messages by bitness. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit e8af03bf9a3281e55b832cd801528392a9a7d9af Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 17:43:09 2019 +0200 x86emul: prepare for AVX512F S/G insns They require getting modrm_reg and sib_index set correctly in the EVEX case, to account for the high 16 [XYZ]MM registers when used as addressing index register. Extend the adjustments to modrm_rm as well, such that x86_insn_modrm() would correctly report register numbers (this was a latent issue only as we don't currently have callers of that function which would care about an EVEX case). The adjustment in turn requires dropping the assertion from decode_gpr() as well as re-introducing the explicit masking, as we now need to actively mask off the high bit when a GPR is meant. _decode_gpr() invocations also need slight adjustments, when invoked in generic code ahead of the main switch(). All other uses of modrm_reg and modrm_rm already get suitably masked where necessary. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 92b80e3e3dfacf389cff797580b3806576051dfd Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 17:42:25 2019 +0200 x86/IRQ: add explicit tracing-enabled check to trace_irq_mask() The setup for calling trace_var() (which itself checks tb_init_done) is non-negligible, and hence a separate outer-most check is warranted. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit acdb58b9b93f6ce2be1442295925a801cba706e6 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 17:32:53 2019 +0200 x86/IRQ: simplify and rename pirq_acktype() Its only caller already has the IRQ descriptor in its hands, so there's no need for the function to re-obtain it. As a result the leading p of its name is no longer appropriate and hence gets dropped. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 6d819cf9e1a6d21f68d9fe840040e89057ced1be Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 17:32:08 2019 +0200 x86/IRQ: improve dump_irqs() Don't log a stray trailing comma. Shorten a few fields. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Roger Pau Monné <roger.pau@xxxxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit f4a09c9377716cd3f3ba18196fe5879be890a4f5 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 16:08:42 2019 +0200 x86emul: support remaining misc AVX512{F,BW} insns This completes support of AVX512BW in the insn emulator, and leaves just the scatter/gather ones open in the AVX512F set. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 65f82d4ce1eada3eb494bb81416bd05b63f73ab2 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 16:08:00 2019 +0200 x86emul: support AVX512{F,_VBMI2} compress/expand insns Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit dcac6de1f5b34d52b5f37c73b85c3b627581d413 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 16:07:01 2019 +0200 x86/vPIC: avoid speculative out of bounds accesses Array indexes used in the I/O port read/write emulation functions are derived from guest controlled values. Where this is not already done, restrict their ranges to limit the side effects of speculative execution. This is part of the speculative hardening effort. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit be15c231e7e351ea8dbcabf62f952537c637343d Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 16:06:27 2019 +0200 x86/vMSI: avoid speculative out of bounds accesses Array indexes used in the MMIO read/write emulation functions are derived from guest controlled values. Restrict their ranges to limit the side effects of speculative execution. Note that the index into .msi_ad[] may also be speculatively out of bounds, by exactly one (indexes 0...3 are possible while the array has just 3 elements). This is not a problem with the current data layout, as such overrun of the array would either touch the next element of the parent array or (for the last entry of the parent array) access the subsequent acc_valid bit array. This is part of the speculative hardening effort. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 1f2ccbd40c85e383799d59f9dfc1cffa5e18c920 Author: Jan Beulich <jbeulich@xxxxxxxx> Date: Thu Jul 4 16:05:18 2019 +0200 x86emul: avoid speculative out of bounds accesses There are a few array accesses here the indexes of which are (at least indirectly) driven by the guest. Use array_access_nospec() to bound such accesses. In the {,_}decode_gpr() cases replace existing guarding constructs. To deal with an otherwise occurring #include cycle, drop the inclusion of asm/x86_emulate.h from asm/processor.h. This include had been introduced for obtaining the struct cpuid_leaf declaration, which has since moved into the x86 helper library. This is part of the speculative hardening effort. Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> Reviewed-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> commit 90bef5822dda473055b8aa466450686e3311bf2d Author: Anthony PERARD <anthony.perard@xxxxxxxxxx> Date: Thu Jul 4 16:04:33 2019 +0200 MAINTAINERS: add Anthony as libxl maintainer Create a new section with only libxl. Signed-off-by: Anthony PERARD <anthony.perard@xxxxxxxxxx> Acked-by: Stefano Stabellini <sstabellini@xxxxxxxxxx> Acked-by: Ian Jackson <ian.jackson@xxxxxxxxxxxxx> Acked-by: Wei Liu <wl@xxxxxxx> commit 782a6b951a2317e1c3ecc81b6d94be09157fc363 Author: Paul Durrant <paul.durrant@xxxxxxxxxx> Date: Thu Jul 4 16:03:47 2019 +0200 xmalloc: stop using a magic '1' in alignment padding Alignment padding inserts a pseudo block header in front of the allocation, sets its size field to the pad size and then ORs in 1, which is equivalent to marking it as a free block, so that xfree() can distinguish it from a real block header. This patch simply replaces the magic '1' with the defined 'FREE_BLOCK' to make it more obvious what's going on. Also, whilst in the neighbourhood, it removes a stray space after a cast. Signed-off-by: Paul Durrant <paul.durrant@xxxxxxxxxx> Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx> commit 12dce7ea5a84e0f107710f8df1cfb2dfe306c793 Author: Juergen Gross <jgross@xxxxxxxx> Date: Thu Jul 4 16:02:52 2019 +0200 x86: make loading of GDT at context switch more modular In preparation for core scheduling, carve out the GDT related functionality (writing GDT related PTEs, loading default of full GDT) into sub-functions. Signed-off-by: Juergen Gross <jgross@xxxxxxxx> Acked-by: Jan Beulich <jbeulich@xxxxxxxx> Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx> (qemu changes not included) _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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