Re: [Xen-devel] [PATCH v2 34/35] xen/arm32: head: Setup HTTBR in enable_mmu() and add missing isb

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Mon, 22 Jul 2019, Julien Grall wrote:
> At the moment, HTTBR is setup in create_page_tables(). This is fine as
> it is called by every CPUs.
> 
> However, such assumption may not hold in the future. To make change
> easier, the HTTBR is not setup in enable_mmu().
> 
> Take the opportunity to add the missing isb() to ensure the HTTBR is
> seen before the MMU is turned on.
> 
> Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
> 
> ---
>     Changes in v2:
>         - Patch added
> ---
>  xen/arch/arm/arm32/head.S | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
> index 6d55a2119a..8a1e272aab 100644
> --- a/xen/arch/arm/arm32/head.S
> +++ b/xen/arch/arm/arm32/head.S
> @@ -373,8 +373,6 @@ create_page_tables:
>          /* Write Xen's PT's paddr into the HTTBR */

This comment needs to be moved


>          ldr   r4, =boot_pgtable
>          add   r4, r4, r10            /* r4 := paddr (boot_pagetable) */
> -        mov   r5, #0                 /* r4:r5 is paddr (boot_pagetable) */
> -        mcrr  CP64(r4, r5, HTTBR)

Interestingly r5 is not clobbered by create_page_tables anymore, we need
to update the comment on top.


>          /* Setup boot_pgtable: */
>          ldr   r1, =boot_second
> @@ -480,6 +478,12 @@ enable_mmu:
>          mcr   CP32(r0, TLBIALLH)     /* Flush hypervisor TLBs */
>          dsb   nsh
>  
> +        ldr   r0, =boot_pgtable
> +        add   r0, r0, r10            /* r0 := paddr (boot_pagetable) */
> +        mov   r1, #0                 /* r0:r1 is paddr (boot_pagetable) */
> +        mcrr  CP64(r0, r1, HTTBR)
> +        isb
> +
>          mrc   CP32(r0, HSCTLR)
>          /* Enable MMU and D-cache */
>          orr   r0, r0, #(SCTLR_Axx_ELx_M|SCTLR_Axx_ELx_C)
> -- 
> 2.11.0
> 

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