[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v10 16/16] microcode/intel: writeback and invalidate cache conditionally
It is needed to mitigate some issues on this specific Broadwell CPU. Signed-off-by: Chao Gao <chao.gao@xxxxxxxxx> --- xen/arch/x86/microcode_intel.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/xen/arch/x86/microcode_intel.c b/xen/arch/x86/microcode_intel.c index bcef668..4e5e7f9 100644 --- a/xen/arch/x86/microcode_intel.c +++ b/xen/arch/x86/microcode_intel.c @@ -305,6 +305,31 @@ static bool is_blacklisted(void) return false; } +static void microcode_quirk(void) +{ + struct cpuinfo_x86 *c; + uint64_t llc_size; + + /* + * Don't refer to current_cpu_data, which isn't fully initialized + * before this stage. + */ + if ( system_state < SYS_STATE_smp_boot ) + return; + + c = ¤t_cpu_data; + llc_size = c->x86_cache_size * 1024ULL; + do_div(llc_size, c->x86_max_cores); + + /* + * To mitigate some issues on this specific Broadwell CPU, writeback and + * invalidate cache regardless of ucode revision. + */ + if ( c->x86 == 6 && c->x86_model == 0x4F && c->x86_mask == 0x1 && + llc_size > 2621440 ) + wbinvd(); +} + static int apply_microcode(const struct microcode_patch *patch) { uint64_t msr_content; @@ -323,6 +348,8 @@ static int apply_microcode(const struct microcode_patch *patch) BUG_ON(local_irq_is_enabled()); + microcode_quirk(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc_intel->bits); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL); -- 1.8.3.1 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxxx https://lists.xenproject.org/mailman/listinfo/xen-devel
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