Re: [Xen-devel] wall clock drift on Coffee Lake / C24x mainboard (HPET broken?), best practices

[Andreas Kinzler <hfp@xxxxxxxxx>]

On 14.11.2019 12:29, Jan Beulich wrote:
> On 14.11.2019 00:10, Andreas Kinzler wrote:
> > I came across the following: https://lkml.org/lkml/2019/8/29/536
> > Could that be the reason for the problem mentioned below? Xen is using
> > HPET as clocksource on the platform/mainboard. Is there an (easy) way to
> > verify if Xen uses PC10?
> In principle this can be obtained via both the xenpm utility and
> the 'c' debug key.
Both xenpm and 'c' debug key show only up to level 7 in Xen 4.10.x 
(unmodified code).
> For Coffee Lake, however, I can't find any
> indication in the SDM that a PC10 residency MSR would exist.
I used turbostat 
(https://github.com/torvalds/linux/blob/master/tools/power/x86/turbostat/turbostat.c) 
as a help. See functions has_c8910_msrs and intel_model_duplicates.
I then added Coffee Lake with PC8/9/10 to do_get_hw_residencies and then 
I got high counts in PC8+PC9 and zero in PC10.
> Hence I can only suggest that you try again with limited or no
> use of C states, to at least get a hint as to a possible
I changed the BIOS setting to a limit of PC7 and it is now running. I 
have to wait for the result. Thanks.
Regards Andreas

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel