Re: [Xen-devel] [PATCH for-4.13] x86/cpuid: Fix Lisbon/Magny-Cours Opterons WRT SSSE3/SSE4A

[Jan Beulich <jbeulich@xxxxxxxx>]

On 19.11.2019 18:00, Andrew Cooper wrote:
> c/s ff66ccefe5 "x86/CPUID: adjust SSEn dependencies" made SSE4A depend on
> SSSE3, but these processors really do have have SSE4A without SSSE3.
> 
> This manifests as an upgrade regression, as the SSE4A feature disappears from
> view.
> 
> Adjust the SSE4A feature to depend on SSE3 rather than SSSE3.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>

Nevertheless a remark:

> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -205,9 +205,10 @@ def crunch_numbers(state):
>          # than to SSE.
>          SSE2: [SSE3, LM, AESNI, PCLMULQDQ, SHA, GFNI],
>  
> -        # Other SSEn each depend on their predecessor versions.
> -        SSE3: [SSSE3],
> -        SSSE3: [SSE4_1, SSE4A],
> +        # Other SSEn each depend on their predecessor versions.  AMD
> +        # Lisbon/Magny-Cours processors implemented SSE4A without SSSE3.
> +        SSE3: [SSSE3, SSE4A],
> +        SSSE3: [SSE4_1],
>          SSE4_1: [SSE4_2],

If we'd be taking the SDM by the word, this would still be too restrictive.
I suppose though it's been more a copy-and-paste effect that has lead to:

"Before an application attempts to use the SIMD subset of SSE3 extensions,
 the application should follow the steps illustrated in Section 11.6.2,
 “Checking for SSE/SSE2 Support.” Next, use the additional step provided
 below:
 • Check that the processor supports the SIMD and x87 SSE3 extensions (if
   CPUID.01H:ECX.SSE3[bit 0] = 1)."

"Before an application attempts to use the SSSE3 extensions, the application
 should follow the steps illustrated in Section 11.6.2, “Checking for
 SSE/SSE2 Support.” Next, use the additional step provided below:
• Check that the processor supports SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1)."

Which would imply SSSE3 only takes SSE2 (and implicitly SSE) as prereq.
As opposed:

"Before an application attempts to use SSE4.1 instructions, the application
 should follow the steps illustrated in Section 11.6.2, “Checking for
 SSE/SSE2 Support.” Next, use the additional step provided below:
 Check that the processor supports SSE4.1 (if
 CPUID.01H:ECX.SSE4_1[bit 19] = 1), SSE3 (if CPUID.01H:ECX.SSE3[bit 0] = 1),
 and SSSE3 (if CPUID.01H:ECX.SSSE3[bit 9] = 1)."

Similar text is there for for SSE4.2, taking additionally SSE4.1 as prereq.

I'll fire off an email to Intel requesting clarification.

Jan

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel