Re: [Xen-devel] [PATCH 1/2] x86/tlbflush: do not toggle the PGE CR4 bit unless necessary

[Jan Beulich <jbeulich@xxxxxxxx>]

On 25.11.2019 18:22, Roger Pau Monne wrote:
> When PCID is not available Xen does a full tlbflush by toggling the
> PGE bit in CR4. This is not necessary if PGE is not enabled, since a
> flush can be performed by writing to CR3 in that case.
> 
> Change the code in do_tlb_flush to only toggle the PGE bit in CR4 if
> it's already enabled, otherwise do the tlb flush by writing to CR3.
> This is relevant when running virtualized, since hypervisors don't
> usually trap accesses to CR3 when using hardware assisted paging, but
> do trap accesses to CR4 specially on AMD hardware, which makes such
> accesses much more expensive.
> 
> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>

Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
with one remark:

> --- a/xen/arch/x86/flushtlb.c
> +++ b/xen/arch/x86/flushtlb.c
> @@ -84,6 +84,7 @@ static void post_flush(u32 t)
>  static void do_tlb_flush(void)
>  {
>      unsigned long flags;
> +    unsigned long cr4;

This would better be merged with the adjacent declaration. Can surely
be done while committing.

Jan

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