Re: [Xen-devel] [PATCH v7 1/3] x86/tlb: introduce a flush HVM ASIDs flag

[Julien Grall <julien@xxxxxxx>]

On 19/03/2020 17:38, Roger Pau Monné wrote:
> On Thu, Mar 19, 2020 at 04:21:23PM +0000, Julien Grall wrote:
> > Hi,
> >
> > On 19/03/2020 15:47, Roger Pau Monne wrote:
> > > diff --git a/xen/include/xen/mm.h b/xen/include/xen/mm.h
> > > index d0d095d9c7..02aad43042 100644
> > > --- a/xen/include/xen/mm.h
> > > +++ b/xen/include/xen/mm.h
> > > @@ -644,7 +644,7 @@ static inline void filtered_flush_tlb_mask(uint32_t 
> > > tlbflush_timestamp)
> > >        if ( !cpumask_empty(&mask) )
> > >        {
> > >            perfc_incr(need_flush_tlb_flush);
> > > -        flush_tlb_mask(&mask);
> > > +        flush_mask(&mask, FLUSH_TLB | FLUSH_HVM_ASID_CORE);
> > A rule of thumb is any modification in common code may impact Arm. This is a
> > case here because the flag and the "new" function are not defined on Arm and
> > therefore going to break the build.
> flush_mask is not a new function, it's just not implemented on ARM I
> guess.
That's why I said it in "" ;).

>  >> Why can't you keep flush_tlb_mask() here?
>
> Because filtered_flush_tlb_mask is used in populate_physmap, and
> changes to the phymap require an ASID flush on AMD hardware.
I am afraid this does not yet explain me why flush_tlb_mask() could not 
be updated so it flush the ASID on AMD hardware.
This would actually match the behavior of flush_tlb_mask() on Arm where 
all the guest TLBs would be removed.
Cheers,

--
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxxxxxxxxx
https://lists.xenproject.org/mailman/listinfo/xen-devel