[Xen-devel] [PATCH] xen/arm: implement GICD_I[S/C]ACTIVER reads

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

This is a simple implementation of GICD_ICACTIVER / GICD_ISACTIVER
reads. It doesn't take into account the latest state of interrupts on
other processors. Only the local processor is up-to-date.

Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxx>
Tested-by: Wei Xu <xuwei5@xxxxxxxxxxxxx>
Tested-by: Peng Fan <peng.fan@xxxxxxx>

diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index 4e60ba15cc..c9755ba45b 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -713,9 +713,38 @@ static int __vgic_v3_distr_common_mmio_read(const char 
*name, struct vcpu *v,
         goto read_as_zero;
 
     /* Read the active status of an IRQ via GICD/GICR is not supported */
-    case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVER):
+    case VRANGE32(GICD_ISACTIVER, GICD_ISACTIVERN):
     case VRANGE32(GICD_ICACTIVER, GICD_ICACTIVERN):
-        goto read_as_zero;
+    {
+        bool invert = false;
+        struct pending_irq *p;
+        unsigned int start_irq, irq;
+
+        if ( reg < GICD_ISACTIVERN )
+            start_irq = (reg - GICD_ISACTIVER) * 8;
+        else
+        {
+            start_irq = (reg - GICD_ICACTIVER) * 8;
+            invert = true;
+        }
+
+        *r = 0;
+
+        /*
+         * The following won't reflect the latest status of interrupts on
+         * other vcpus.
+         */
+        for ( irq = start_irq; irq < start_irq + 32; irq++ )
+        {
+            p = irq_to_pending(v, irq);
+            if ( p != NULL && test_bit(GIC_IRQ_GUEST_ACTIVE, &p->status) )
+                *r |= 1 << (irq - start_irq);
+        }
+        if ( invert )
+            *r = ~(*r);
+
+        return 1;
+    }
 
     case VRANGE32(GICD_IPRIORITYR, GICD_IPRIORITYRN):
     {


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