Re: [PATCH v2] x86/idle: prevent entering C6 with in service interrupts on Intel

[Roger Pau Monné <roger.pau@xxxxxxxxxx>]

On Mon, May 11, 2020 at 11:38:49AM +0100, Andrew Cooper wrote:
> On 11/05/2020 11:17, Roger Pau Monne wrote:
> > Apply a workaround for Intel errata CLX30: "A Pending Fixed Interrupt
> > May Be Dispatched Before an Interrupt of The Same Priority Completes".
> >
> > It's not clear which models are affected, as the errata is listed in
> > the "Second Generation Intel Xeon Scalable Processors" specification
> > update, but the issue has been seen as far back as Nehalem processors.
> 
> Really?  I'm only aware of it being Haswell and later.
> 
> CLX30 was just one single example I gave you.  It is public in all the
> specification updates going backwards, and is for example SKX100, BDX99 etc.

Right, will update accordingly then.

> > Apply the workaround to all Intel processors, the condition can be
> > relaxed later.
> 
> Nothing in the code checks ISR, so we're applying "no power saving"
> unilaterally rather than in the very rare corner case that it occurs.

We don't check ISR directly, but instead the stack of pending
interrupts to EOI, which should match the vectors pending in the ISR?

As vectors that can be masked are not held pending in the ISR. I can
check ISR directly if that's any better, but AFAICT using
cpu_has_pending_apic_eoi is equally effective and faster.

> I'm also not aware of it affecting Atom processors.
> 
> This will cripple anything running on battery power, and is therefore
> not an appropriate fix in this form.

TBH, I've tried it in it's current form and it doesn't trigger that
often.

Thanks, Roger.