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Re: [PATCH] x86/idle: prevent entering C3/C6 on some Intel CPUs due to errata

To: Roger Pau Monne <roger.pau@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Date: Fri, 22 May 2020 10:17:07 +0100
Cc: Wei Liu <wl@xxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>
Delivery-date: Fri, 22 May 2020 09:17:14 +0000
List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 22/05/2020 09:09, Roger Pau Monne wrote:
> Apply a workaround for errata BA80, AAK120, AAM108, AAO67, BD59,
> AAY54: Rapid Core C3/C6 Transition May Cause Unpredictable System
> Behavior.
>
> Limit maximum C state to C2 when SMT is enabled on the affected CPUs.

C1

> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>

Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

A fix for this is long overdue.

~Andrew

References:
- [PATCH] x86/idle: prevent entering C3/C6 on some Intel CPUs due to errata
  - From: Roger Pau Monne

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