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Re: [PATCH for-4.14 1/2] x86/passthrough: do not assert edge triggered GSIs for PVH dom0


  • To: Roger Pau Monne <roger.pau@xxxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Wed, 10 Jun 2020 13:29:40 +0100
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  • Cc: Wei Liu <wl@xxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, paul@xxxxxxx
  • Delivery-date: Wed, 10 Jun 2020 12:29:56 +0000
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  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 10/06/2020 12:51, Roger Pau Monne wrote:
> Edge triggered interrupts do not assert the line, so the handling done
> in Xen should also avoid asserting it. Asserting the line prevents
> further edge triggered interrupts on the same vIO-APIC pin from being
> delivered, since the line is not de-asserted.
>
> One case of such kind of interrupt is the RTC timer, which is edge
> triggered and available to a PVH dom0. Note this should not affect
> domUs, as it only modifies the behavior of IDENTITY_GSI kind of passed
> through interrupts.
>
> Signed-off-by: Roger Pau Monné <roger.pau@xxxxxxxxxx>

Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>



 


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