[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 2/7] x86/vmx: add Intel PT MSR definitions


  • To: Michał Leszczyński <michal.leszczynski@xxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Mon, 22 Jun 2020 14:35:47 +0200
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mDMm5egDgN3EYbBLG3djJ7VTHj0NgvGfUORgRWj74og=; b=ciDUrRFH57g29/kuErccHMdODURGYOntHkK3agpU+Mm3xWxJizEdoLt+cLHmDC98wu3lzISymZ+zAR0bjWgtO/LD4LHpqBDdeNvpILkygg8maBxkPhS56YxYYcg/A9b9mZjWVAWF/zbSoovY0OYORsmCRCToYAjCsMLJwQA2tFlkhR5njFpe881jWObdjW6MxtZkp+Yp779kAuCOzZdbcl32qkK53eoO4yd/AbpYekAPO+jdirSzJR91iOubfT5/3VwC383b8EulS9nBB0WwWXwiaZQ76LfEY6SE1AG1W4n7cwKb2z+qDFLrb2VvcSYVc5BvcZdYywRceTSxuyuxJw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TUegx7t13yIqVFmrh6EF9tAeP+6Fq+p+YFuSl6HDNEX2JJE9y0ZHKE3QuZgtnBteRktXVr62f5O41iO0Qqtfj5/O3ehogCh5M4sndiJARi/XEgVpL9zvVeTstdLbMNcD7kGjYTsC7eW0kQmTDvsQdfCGCd7RRu4xSGFo2ttH6unqHcy2F77NAgMICRFaLI9dwxdJbuAwDDRoVuWB0kEY3vwaFyxjtrRg7g4C30QOKTeXluIOxezT5X2VSvZoqCeJzGqC+0uUC8qPlhbrxVTMBi+9YQlLX/uuqSrjlGCbllrt2KJ84QJDXSTSE92II23O6YawCvXWLHniBy0aSpw6nQ==
  • Authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=suse.com;
  • Cc: "Kang, Luwei" <luwei.kang@xxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Tamas K Lengyel <tamas.k.lengyel@xxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Delivery-date: Mon, 22 Jun 2020 12:36:22 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 19.06.2020 01:39, Michał Leszczyński wrote:
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -621,4 +621,41 @@
>  #define MSR_PKGC9_IRTL                       0x00000634
>  #define MSR_PKGC10_IRTL                      0x00000635
>  
> +/* Intel PT MSRs */
> +#define MSR_RTIT_OUTPUT_BASE           0x00000560
> +#define MSR_RTIT_OUTPUT_MASK           0x00000561
> +#define MSR_RTIT_CTL                   0x00000570
> +#define RTIT_CTL_TRACEEN               (_AC(1, ULL) << 0)
> +#define RTIT_CTL_CYCEN                 (_AC(1, ULL) << 1)
> +#define RTIT_CTL_OS                    (_AC(1, ULL) << 2)
> +#define RTIT_CTL_USR                   (_AC(1, ULL) << 3)
> +#define RTIT_CTL_PWR_EVT_EN            (_AC(1, ULL) << 4)
> +#define RTIT_CTL_FUP_ON_PTW            (_AC(1, ULL) << 5)
> +#define RTIT_CTL_FABRIC_EN             (_AC(1, ULL) << 6)
> +#define RTIT_CTL_CR3_FILTER            (_AC(1, ULL) << 7)
> +#define RTIT_CTL_TOPA                  (_AC(1, ULL) << 8)
> +#define RTIT_CTL_MTC_EN                (_AC(1, ULL) << 9)
> +#define RTIT_CTL_TSC_EN                (_AC(1, ULL) << 10)
> +#define RTIT_CTL_DIS_RETC              (_AC(1, ULL) << 11)
> +#define RTIT_CTL_PTW_EN                (_AC(1, ULL) << 12)
> +#define RTIT_CTL_BRANCH_EN             (_AC(1, ULL) << 13)
> +#define RTIT_CTL_MTC_FREQ_OFFSET       14
> +#define RTIT_CTL_MTC_FREQ              (0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET)

This was a fair step in the right direction, but you've missed
some instances (like here) wanting to use _AC(), and you've
also not moved the whole block up above the legacy line. As
Andrew's "x86/msr: Disallow access to Processor Trace MSRs" is
likely to go in before 4.14 in some form, you'll want to
re-base over it eventually anyway. You may want to take a look
there right away, to see where in the header to place your
addition.

If you look further up in the file you'll also notice how we
try to visually separate MSR numbers from bit-within-MSR
definitions.

Finally I'd also like to ask that you omit all RTIT_CTL_*_OFFSET
values. Only the _OFFSET-less #define-s should really be needed
- see MASK_EXTR() and MASK_INSR() in case right now you're using
these for some open-coded shifting ...

Jan



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.