[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH] xen/arm: Add Cortex-A73 erratum 858921 workaround
- To: Julien Grall <julien@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, "sstabellini@xxxxxxxxxx" <sstabellini@xxxxxxxxxx>
- From: Penny Zheng <Penny.Zheng@xxxxxxx>
- Date: Tue, 10 Nov 2020 09:31:37 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G9IZsptPU/gTSzuYimH3onRmy2KghqqHJrBnEnUhsOQ=; b=lmoH92UWeS487QAwi2yst0/njd10We5Z7NQ65aFZB2YoRChzoKwCkWMZD4JK+z+PaMxsPvM8Kp82IlSaisyxaZmPUgkyYU1qh6VAtgvYG3zd0oykRvS4j5wpWqFEbRlIdN3Yb+4OBrjw2QbbaIgTcW7avDz/Y/SoXHFFoQnn/QjJ5rDVanerarxtAKRqnQhP/y3Xxe8OxlWYocA4Lhwkz81yihnYAK77zM1OfdJTDodF3vnQRc0s2dH48QayzIRyLox2goDWsUB/ItlTUT6J3JMky6iGAxNPMBqzHX/G0knyOlfS/aSub9hOhX+otJuCQQCFM4v4k0BBJPM7Y+Bkaw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=P55FmaBW4vOANJHuWDOjw2RlcVhicLAlBp9nxufjO/KjeyBitgPQKEVHBN6nkiVW/o+7ZjbTyvzTCfBHl4zWDCm2V6vsuW1dH/bUAdY5kiqbGyLiNlF8CNbwPZ2OWajPhMWAaB7zL5JpG0jHNPT9vKMED2hKRD9yATBBxev+0XhwEe/3JQ8SrYpgSO9aP+t1J7ZlpLMequE3zt0PQc6ZTt/PNCqlgWp+OXEm7k+HoL26QO3fDRuvkHid5NujQ5eaml0tCe5iU0qvqT2Jt1dm2lg4HD5Jwm0zGlVGSMs+ZDbqa56s8PwbqS78AZ2GYHwBHYEpEaJYWDNSAInfaCwTHA==
- Authentication-results-original: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=arm.com;
- Cc: Andre Przywara <Andre.Przywara@xxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Wei Chen <Wei.Chen@xxxxxxx>, Kaly Xin <Kaly.Xin@xxxxxxx>, nd <nd@xxxxxxx>
- Delivery-date: Tue, 10 Nov 2020 09:32:05 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=arm.com;
- Thread-index: AQHWtnF2vBhY4+4fg0iJYr/0WqjXm6m/tA6AgAFmnRA=
- Thread-topic: [PATCH] xen/arm: Add Cortex-A73 erratum 858921 workaround
> -----Original Message-----
> From: Julien Grall <julien@xxxxxxx>
> Sent: Monday, November 9, 2020 8:04 PM
> To: Penny Zheng <Penny.Zheng@xxxxxxx>; xen-devel@xxxxxxxxxxxxxxxxxxxx;
> sstabellini@xxxxxxxxxx
> Cc: Andre Przywara <Andre.Przywara@xxxxxxx>; Bertrand Marquis
> <Bertrand.Marquis@xxxxxxx>; Wei Chen <Wei.Chen@xxxxxxx>; Kaly Xin
> <Kaly.Xin@xxxxxxx>; nd <nd@xxxxxxx>
> Subject: Re: [PATCH] xen/arm: Add Cortex-A73 erratum 858921 workaround
>
> Hi,
>
> On 09/11/2020 08:21, Penny Zheng wrote:
> > CNTVCT_EL0 or CNTPCT_EL0 counter read in Cortex-A73 (all versions)
> > might return a wrong value when the counter crosses a 32bit boundary.
> >
> > Until now, there is no case for Xen itself to access CNTVCT_EL0, and
> > it also should be the Guest OS's responsibility to deal with this
> > part.
> >
> > But for CNTPCT, there exists several cases in Xen involving reading
> > CNTPCT, so a possible workaround is that performing the read twice,
> > and to return one or the other depending on whether a transition has
> > taken place.
> >
> > Signed-off-by: Penny Zheng <penny.zheng@xxxxxxx>
>
> Acked-by: Julien Grall <jgrall@xxxxxxxxxx>
>
Thank you. 😉
> On a related topic, do we need a fix similar to Linux commit 75a19a0202db
> "arm64: arch_timer: Ensure counter register reads occur with seqlock held"?
>
Sure, I'll check this commit and talk with my teams for further work.
Cheers
--
Penny Zheng
> Cheers,
>
> --
> Julien Grall
|
