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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v4 0/8] xen/arm: Emulate ID registers
Hi Stefano, > On 17 Dec 2020, at 23:47, Stefano Stabellini <sstabellini@xxxxxxxxxx> wrote: > > On Thu, 17 Dec 2020, Bertrand Marquis wrote: >> The goal of this serie is to emulate coprocessor ID registers so that >> Xen only publish to guest features that are supported by Xen and can >> actually be used by guests. >> One practical example where this is required are SVE support which is >> forbidden by Xen as it is not supported, but if Linux is compiled with >> it, it will crash on boot. An other one is AMU which is also forbidden >> by Xen but one Linux compiled with it would crash if the platform >> supports it. >> >> To be able to emulate the coprocessor registers defining what features >> are supported by the hardware, the TID3 bit of HCR must be disabled and >> Xen must emulated the values of those registers when an exception is >> catched when a guest is accessing it. >> >> This serie is first creating a guest cpuinfo structure which will >> contain the values that we want to publish to the guests and then >> provides the proper emulationg for those registers when Xen is getting >> an exception due to an access to any of those registers. >> >> This is a first simple implementation to solve the problem and the way >> to define the values that we provide to guests and which features are >> disabled will be in a future patchset enhance so that we could decide >> per guest what can be used or not and depending on this deduce the bits >> to activate in HCR and the values that we must publish on ID registers. > > As per our discussion I think we want to add this to the series. Fully agree. > > --- > > xen/arm: clarify support status for various ARMv8.x CPUs > > ARMv8.1+ is not security supported for now, as it would require more > investigation on hardware features that Xen has to hide from the guest. > > Signed-off-by: Stefano Stabellini <stefano.stabellini@xxxxxxxxxx> Reviewed-by: Bertrand Marquis <bertrand.marquis@xxxxxxx> Cheers Bertrand > > diff --git a/SUPPORT.md b/SUPPORT.md > index ab02aca5f4..d95ce3a411 100644 > --- a/SUPPORT.md > +++ b/SUPPORT.md > @@ -37,7 +37,8 @@ supported in this document. > > ### ARM v8 > > - Status: Supported > + Status, ARMv8.0: Supported > + Status, ARMv8.1+: Supported, not security supported > Status, Cortex A57 r0p0-r1p1: Supported, not security supported > > For the Cortex A57 r0p0 - r1p1, see Errata 832075.
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