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Re: [PATCH] x86/Intel: insert Tiger Lake model numbers


  • To: Jan Beulich <jbeulich@xxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
  • Date: Mon, 21 Dec 2020 16:56:10 +0000
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  • Cc: Wei Liu <wl@xxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Delivery-date: Mon, 21 Dec 2020 16:56:21 +0000
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On 21/12/2020 16:50, Jan Beulich wrote:
> Both match prior generation processors as far as LBR and C-state MSRs
> go (SDM rev 073). The if_pschange_mc erratum, according to the spec
> update, is not applicable.
>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>
> --- a/xen/arch/x86/acpi/cpu_idle.c
> +++ b/xen/arch/x86/acpi/cpu_idle.c
> @@ -183,6 +183,9 @@ static void do_get_hw_residencies(void *
>      /* Ice Lake */
>      case 0x7D:
>      case 0x7E:
> +    /* Tiger Lake */
> +    case 0x8C:
> +    case 0x8D:
>      /* Kaby Lake */
>      case 0x8E:
>      case 0x9E:
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2436,6 +2436,12 @@ static bool __init has_if_pschange_mc(vo
>          return true;
>  
>          /*
> +         * Newer Core processors are not vulnerable.
> +         */
> +    case 0x8c: /* Tiger Lake */
> +    case 0x8d: /* Tiger Lake */
> +

This hunk should be dropped.  TGL should enumerate
ARCH_CAPS_IF_PSCHANGE_MC_NO and take the early exit path.

If it doesn't, we need to know (i.e. hitting the default case), and I'll
do even more pestering to have ucode fixed.

Others Acked-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

> +        /*
>           * Atom processors are not vulnerable.
>           */
>      case 0x1c: /* Pineview */
> @@ -2776,6 +2782,8 @@ static const struct lbr_info *last_branc
>          case 0x7a:
>          /* Ice Lake */
>          case 0x7d: case 0x7e:
> +        /* Tiger Lake */
> +        case 0x8c: case 0x8d:
>          /* Tremont */
>          case 0x86:
>          /* Kaby Lake */




 


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