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Re: [PATCH] do not p2m_invalidate_root when iommu_use_hap_pt

Hi Stefano,

On 04/08/2021 18:41, Stefano Stabellini wrote:
On Wed, 4 Aug 2021, Julien Grall wrote:
Hi Stefano,

On 04/08/2021 01:08, Stefano Stabellini wrote:
diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index caf17174b8..125a9281fc 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -105,6 +105,13 @@ void do_sysreg(struct cpu_user_regs *regs,
        case HSR_SYSREG_DCISW:
        case HSR_SYSREG_DCCSW:
        case HSR_SYSREG_DCCISW:
+        if ( iommu_use_hap_pt(current->domain) )
+        {
+            gdprintk(XENLOG_ERR,
+                     "d%u uses set/way cache flushes with the IOMMU on.
cannot work. Replace set/way instructions with dc [ci]vac and retry.
Injecting exception into the guest now.\n",

This line would be far too long to print on the serial. I think you want
add a few newline here.

Fair enough but I'll try to keep most info on the same line because
otherwise with a dom0less boot it can get confusing. I suggest:

I am not quite too sure to understand why it would get confusing with
dom0less. Can you give an example?

I was doing tests with the error messages before implementing the undef
exception injection. This is the output of a regular domU (not
dom0less): https://pastebin.com/Wytg660j

The entire message in this test should be:

(XEN) d1v0 uses set/way cache flushes with the IOMMU on. It cannot work.
(XEN) Replace them with dc [ci]vac and retry.

But actually the first line gets eaten, so we only see:

(XEN) Replace them with dc [ci]vac and retry.

several times at the bottom of the logs.

That's most likely because you are hitting the ratelimit. However, writing a 80+ line is almost the wrong way to go. This making a lot more difficult to serial the console output...

Looking at the output, I think you can shorten to:

"The cache should be flushed by VA rather than by set/way."

At least this would make clear that using them even without the IOMMU is a bad idea for performance reason.


Julien Grall



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