[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
- To: Tianyu Lan <ltykernel@xxxxxxxxx>, KY Srinivasan <kys@xxxxxxxxxxxxx>, Haiyang Zhang <haiyangz@xxxxxxxxxxxxx>, Stephen Hemminger <sthemmin@xxxxxxxxxxxxx>, "wei.liu@xxxxxxxxxx" <wei.liu@xxxxxxxxxx>, Dexuan Cui <decui@xxxxxxxxxxxxx>, "tglx@xxxxxxxxxxxxx" <tglx@xxxxxxxxxxxxx>, "mingo@xxxxxxxxxx" <mingo@xxxxxxxxxx>, "bp@xxxxxxxxx" <bp@xxxxxxxxx>, "x86@xxxxxxxxxx" <x86@xxxxxxxxxx>, "hpa@xxxxxxxxx" <hpa@xxxxxxxxx>, "dave.hansen@xxxxxxxxxxxxxxx" <dave.hansen@xxxxxxxxxxxxxxx>, "luto@xxxxxxxxxx" <luto@xxxxxxxxxx>, "peterz@xxxxxxxxxxxxx" <peterz@xxxxxxxxxxxxx>, "konrad.wilk@xxxxxxxxxx" <konrad.wilk@xxxxxxxxxx>, "boris.ostrovsky@xxxxxxxxxx" <boris.ostrovsky@xxxxxxxxxx>, "jgross@xxxxxxxx" <jgross@xxxxxxxx>, "sstabellini@xxxxxxxxxx" <sstabellini@xxxxxxxxxx>, "joro@xxxxxxxxxx" <joro@xxxxxxxxxx>, "will@xxxxxxxxxx" <will@xxxxxxxxxx>, "davem@xxxxxxxxxxxxx" <davem@xxxxxxxxxxxxx>, "kuba@xxxxxxxxxx" <kuba@xxxxxxxxxx>, "jejb@xxxxxxxxxxxxx" <jejb@xxxxxxxxxxxxx>, "martin.petersen@xxxxxxxxxx" <martin.petersen@xxxxxxxxxx>, "arnd@xxxxxxxx" <arnd@xxxxxxxx>, "hch@xxxxxx" <hch@xxxxxx>, "m.szyprowski@xxxxxxxxxxx" <m.szyprowski@xxxxxxxxxxx>, "robin.murphy@xxxxxxx" <robin.murphy@xxxxxxx>, "thomas.lendacky@xxxxxxx" <thomas.lendacky@xxxxxxx>, "brijesh.singh@xxxxxxx" <brijesh.singh@xxxxxxx>, "ardb@xxxxxxxxxx" <ardb@xxxxxxxxxx>, Tianyu Lan <Tianyu.Lan@xxxxxxxxxxxxx>, "pgonda@xxxxxxxxxx" <pgonda@xxxxxxxxxx>, "martin.b.radev@xxxxxxxxx" <martin.b.radev@xxxxxxxxx>, "akpm@xxxxxxxxxxxxxxxxxxxx" <akpm@xxxxxxxxxxxxxxxxxxxx>, "kirill.shutemov@xxxxxxxxxxxxxxx" <kirill.shutemov@xxxxxxxxxxxxxxx>, "rppt@xxxxxxxxxx" <rppt@xxxxxxxxxx>, "sfr@xxxxxxxxxxxxxxxx" <sfr@xxxxxxxxxxxxxxxx>, "saravanand@xxxxxx" <saravanand@xxxxxx>, "krish.sadhukhan@xxxxxxxxxx" <krish.sadhukhan@xxxxxxxxxx>, "aneesh.kumar@xxxxxxxxxxxxx" <aneesh.kumar@xxxxxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, "rientjes@xxxxxxxxxx" <rientjes@xxxxxxxxxx>, "hannes@xxxxxxxxxxx" <hannes@xxxxxxxxxxx>, "tj@xxxxxxxxxx" <tj@xxxxxxxxxx>
- From: Michael Kelley <mikelley@xxxxxxxxxxxxx>
- Date: Fri, 13 Aug 2021 20:26:21 +0000
- Accept-language: en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microsoft.com; dmarc=pass action=none header.from=microsoft.com; dkim=pass header.d=microsoft.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=uSjZFw4IYdkuV55KvpmYCB+d8Z/zYCy0L7lVeoa3LBM=; b=K947ukP0YWv+I2nRFEcIidwNXTLXNVTGv5Z96kLDRrmBSJQJB+pwI7NF4drCuTLNN0Pr61OAhRGh0vR9x5wQBd8fJayjMT4FyNUjfAjvC5spVhH8TyRL8Adr35FZKB5FY4l1U3tkERSWMmJxmOwWzbHEfj6YQbhN6arVypA0PWxCeehLOfMaSAvLCUIxB/KkiUfR+M2APQElmRzCq+0N1VeI7Af9/kQz/tMu7M/QBIHFyfvnTumQV7WBpzVgeNcVj1gCCNeJLx82gnltOaQUa+HU675I+Ig0zV6crusNPtGjcysAULQt5awd8WMavZvY8BTcKcJ/atkjX8XdmtBGag==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=A6g6l9cYis25WihgKlGKU/RZDzLQjOKNlvRAHPr3qeWLroP+nVKXkTefKHtCJYvIKHnQmTMlaBXOQ3GRPa6EXXTGKP9Eh1Y7VaMjMsfrY7Acj0/7MMaX2tKAF0EndebJNjhNBk8dIITXIsrtXjz0CbhbSMYhZASakOTK4C3mZ4VOyMl6ldknmeFgY+z6uIqxTCgmY560r3aUrChk0p9AuD1y0rzLFwHqse4WR/OLP5ZYxdqhFlQe54yw/7HvaSpFoGHrzf/MyNZD7SRvKTg2Ao6tJpuh+vNPV1+HFahiTvRUywNJ0SNb5LiWRap7V7sYPKzgm9fzJeUGOj6N3q+PFA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microsoft.com;
- Cc: "iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx" <iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx>, "linux-arch@xxxxxxxxxxxxxxx" <linux-arch@xxxxxxxxxxxxxxx>, "linux-hyperv@xxxxxxxxxxxxxxx" <linux-hyperv@xxxxxxxxxxxxxxx>, "linux-kernel@xxxxxxxxxxxxxxx" <linux-kernel@xxxxxxxxxxxxxxx>, "linux-scsi@xxxxxxxxxxxxxxx" <linux-scsi@xxxxxxxxxxxxxxx>, "netdev@xxxxxxxxxxxxxxx" <netdev@xxxxxxxxxxxxxxx>, vkuznets <vkuznets@xxxxxxxxxx>, "parri.andrea@xxxxxxxxx" <parri.andrea@xxxxxxxxx>, "dave.hansen@xxxxxxxxx" <dave.hansen@xxxxxxxxx>
- Delivery-date: Fri, 13 Aug 2021 20:26:52 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Msip_labels: MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ActionId=d2377fda-39f2-4403-a606-910723ff0f1f;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_ContentBits=0;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Enabled=true;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Method=Standard;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_Name=Internal;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SetDate=2021-08-13T18:49:42Z;MSIP_Label_f42aa342-8706-4288-bd11-ebb85995028c_SiteId=72f988bf-86f1-41af-91ab-2d7cd011db47;
- Thread-index: AQHXjUfuQqXPk5/9iUqTH41i8so9wqtxzWQQgAAaltA=
- Thread-topic: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
From: Michael Kelley <mikelley@xxxxxxxxxxxxx> Sent: Friday, August 13, 2021
12:31 PM
> To: Tianyu Lan <ltykernel@xxxxxxxxx>; KY Srinivasan <kys@xxxxxxxxxxxxx>;
> Haiyang Zhang <haiyangz@xxxxxxxxxxxxx>;
> Stephen Hemminger <sthemmin@xxxxxxxxxxxxx>; wei.liu@xxxxxxxxxx; Dexuan Cui
> <decui@xxxxxxxxxxxxx>;
> tglx@xxxxxxxxxxxxx; mingo@xxxxxxxxxx; bp@xxxxxxxxx; x86@xxxxxxxxxx;
> hpa@xxxxxxxxx; dave.hansen@xxxxxxxxxxxxxxx;
> luto@xxxxxxxxxx; peterz@xxxxxxxxxxxxx; konrad.wilk@xxxxxxxxxx;
> boris.ostrovsky@xxxxxxxxxx; jgross@xxxxxxxx;
> sstabellini@xxxxxxxxxx; joro@xxxxxxxxxx; will@xxxxxxxxxx;
> davem@xxxxxxxxxxxxx; kuba@xxxxxxxxxx; jejb@xxxxxxxxxxxxx;
> martin.petersen@xxxxxxxxxx; arnd@xxxxxxxx; hch@xxxxxx;
> m.szyprowski@xxxxxxxxxxx; robin.murphy@xxxxxxx;
> thomas.lendacky@xxxxxxx; brijesh.singh@xxxxxxx; ardb@xxxxxxxxxx; Tianyu Lan
> <Tianyu.Lan@xxxxxxxxxxxxx>;
> pgonda@xxxxxxxxxx; martin.b.radev@xxxxxxxxx; akpm@xxxxxxxxxxxxxxxxxxxx;
> kirill.shutemov@xxxxxxxxxxxxxxx;
> rppt@xxxxxxxxxx; sfr@xxxxxxxxxxxxxxxx; saravanand@xxxxxx;
> krish.sadhukhan@xxxxxxxxxx;
> aneesh.kumar@xxxxxxxxxxxxx; xen-devel@xxxxxxxxxxxxxxxxxxxx;
> rientjes@xxxxxxxxxx; hannes@xxxxxxxxxxx;
> tj@xxxxxxxxxx
> Cc: iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx; linux-arch@xxxxxxxxxxxxxxx;
> linux-hyperv@xxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-scsi@xxxxxxxxxxxxxxx; netdev@xxxxxxxxxxxxxxx;
> vkuznets <vkuznets@xxxxxxxxxx>;
> parri.andrea@xxxxxxxxx; dave.hansen@xxxxxxxxx
> Subject: RE: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
>
> From: Tianyu Lan <ltykernel@xxxxxxxxx> Sent: Monday, August 9, 2021 10:56 AM
> > Subject: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
>
> See previous comments about tag in the Subject line.
>
> > Hyper-V provides GHCB protocol to write Synthetic Interrupt
> > Controller MSR registers in Isolation VM with AMD SEV SNP
> > and these registers are emulated by hypervisor directly.
> > Hyper-V requires to write SINTx MSR registers twice. First
> > writes MSR via GHCB page to communicate with hypervisor
> > and then writes wrmsr instruction to talk with paravisor
> > which runs in VMPL0. Guest OS ID MSR also needs to be set
> > via GHCB.
> >
> > Signed-off-by: Tianyu Lan <Tianyu.Lan@xxxxxxxxxxxxx>
> > ---
> > Change since v1:
> > * Introduce sev_es_ghcb_hv_call_simple() and share code
> > between SEV and Hyper-V code.
> > ---
> > arch/x86/hyperv/hv_init.c | 33 ++-------
> > arch/x86/hyperv/ivm.c | 110 +++++++++++++++++++++++++++++
> > arch/x86/include/asm/mshyperv.h | 78 +++++++++++++++++++-
> > arch/x86/include/asm/sev.h | 3 +
> > arch/x86/kernel/cpu/mshyperv.c | 3 +
> > arch/x86/kernel/sev-shared.c | 63 ++++++++++-------
> > drivers/hv/hv.c | 121 ++++++++++++++++++++++----------
> > include/asm-generic/mshyperv.h | 12 +++-
> > 8 files changed, 329 insertions(+), 94 deletions(-)
> >
> > diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
> > index b3683083208a..ab0b33f621e7 100644
> > --- a/arch/x86/hyperv/hv_init.c
> > +++ b/arch/x86/hyperv/hv_init.c
> > @@ -423,7 +423,7 @@ void __init hyperv_init(void)
> > goto clean_guest_os_id;
> >
> > if (hv_isolation_type_snp()) {
> > - ms_hyperv.ghcb_base = alloc_percpu(void *);
> > + ms_hyperv.ghcb_base = alloc_percpu(union hv_ghcb __percpu *);
>
> union hv_ghcb isn't defined. It is not added until patch 6 of the series.
>
Ignore this comment. My mistake.
Michael
|