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Re: [PATCH 5/9] vpci/header: Implement guest BAR register handlers
- To: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@xxxxxxxx>, Oleksandr Andrushchenko <andr2000@xxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Wed, 8 Sep 2021 17:29:52 +0200
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- Cc: "julien@xxxxxxx" <julien@xxxxxxx>, "sstabellini@xxxxxxxxxx" <sstabellini@xxxxxxxxxx>, Oleksandr Tyshchenko <Oleksandr_Tyshchenko@xxxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Artem Mygaiev <Artem_Mygaiev@xxxxxxxx>, "roger.pau@xxxxxxxxxx" <roger.pau@xxxxxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Rahul Singh <rahul.singh@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 08 Sep 2021 15:30:10 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 08.09.2021 17:14, Oleksandr Andrushchenko wrote:
> On 08.09.21 17:46, Jan Beulich wrote:
>> On 08.09.2021 15:33, Oleksandr Andrushchenko wrote:
>>> static void guest_bar_write(const struct pci_dev *pdev, unsigned int reg,
>>> uint32_t val, void *data)
>>> {
>>> struct vpci_bar *bar = data;
>>> bool hi = false;
>>>
>>> if ( bar->type == VPCI_BAR_MEM64_HI )
>>> {
>>> ASSERT(reg > PCI_BASE_ADDRESS_0);
>>> bar--;
>>> hi = true;
>>> }
>>> else
>>> {
>>> val &= PCI_BASE_ADDRESS_MEM_MASK;
>>> val |= bar->type == VPCI_BAR_MEM32 ? PCI_BASE_ADDRESS_MEM_TYPE_32
>>> : PCI_BASE_ADDRESS_MEM_TYPE_64;
>>> val |= bar->prefetchable ? PCI_BASE_ADDRESS_MEM_PREFETCH : 0;
>>> }
>>>
>>> bar->guest_addr &= ~(0xffffffffull << (hi ? 32 : 0));
>
> Do you think this needs to be 0xfffffffful, not 0xffffffffull?
>
> e.g. s/ull/ul
If guest_addr is uint64_t then ull would seem more correct to me,
especially when considering (hypothetical?) 32-bit architectures
potentially wanting to use this code.
Jan
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