[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 08/11] vpci/header: Emulate PCI_COMMAND register for guests


  • To: Jan Beulich <jbeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • From: Oleksandr Andrushchenko <Oleksandr_Andrushchenko@xxxxxxxx>
  • Date: Tue, 2 Nov 2021 14:10:24 +0000
  • Accept-language: en-US
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=epam.com; dmarc=pass action=none header.from=epam.com; dkim=pass header.d=epam.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AXVVfRUVIe3AEfm6BKwbiddAkI/UN6/DqRNxSZDBYUQ=; b=EY4OyKeV3h4jVmguLDziIICRVXvpo6Ssfq6gi7jgTPDnM28mPY9JMzsvaZSXPY0+++YPDMVQHBB0BAGl6E1YrSmbV6uOhghZqor4hUHa+bovnrIpJ5UqXQhd/RX9qnyHqMrHsQybBsLBkCr5BuezQ909zAZdI+Ykmiysk19ANnY8ghGi0AiakIYeXQ2rNFWQNC6CZ8sqgzvXYerITDSzn5KxxdmNlRh7nVFhkUy7zHEBELLCcAaKtUPossx/zSanOsQ7LfUfA1OcjkMQV489vSRimCEES3NKzyNq7YGe+rm2ZWfS/NtktOcXNBgSgKX3KxgVF8j6kitpB0iS0QcIxw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dLvoRsgayFjWveWlf2Ri6u3rT6A0woHryP/B1gkmbHLA2fXqCwN69hhOdkJDEVucD3w4zV67R1zNXNND5XFVlUA9DqZskFv4beidGv7zKpFI0slwKm+BbQ6+oOYWRXp6a2mKreZ9eHyCJrtcojB4EpM+moSvU4722P8JZD9Ge7l2NpZkl7vHbd0TC65RZwertpGKHa/XKvArAdyyfuh997UCVlYG9A4GhVgwLkC5lUee4Kef3O6wjE2PiuABc3EdE0zpo9ElwYnjQvcU8B08XEXHKTZBTvFk3bazxU9vE6uBebRl3zetH93fJDAU75LqTKlEIyDuALshNBTowDFcMg==
  • Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, "julien@xxxxxxx" <julien@xxxxxxx>, "sstabellini@xxxxxxxxxx" <sstabellini@xxxxxxxxxx>, Oleksandr Tyshchenko <Oleksandr_Tyshchenko@xxxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Artem Mygaiev <Artem_Mygaiev@xxxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Rahul Singh <rahul.singh@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Oleksandr Andrushchenko <Oleksandr_Andrushchenko@xxxxxxxx>
  • Delivery-date: Tue, 02 Nov 2021 14:10:54 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Thread-index: AQHXtdAkq8Qmwxr3HUWTio8KWsEpvKvlQ6KAgAsHq4CAAAimAIAAIt2AgAAEUIA=
  • Thread-topic: [PATCH v3 08/11] vpci/header: Emulate PCI_COMMAND register for guests


On 02.11.21 15:54, Jan Beulich wrote:
> On 02.11.2021 12:50, Roger Pau Monné wrote:
>> On Tue, Nov 02, 2021 at 12:19:13PM +0100, Jan Beulich wrote:
>>> On 26.10.2021 12:52, Roger Pau Monné wrote:
>>>> On Thu, Sep 30, 2021 at 10:52:20AM +0300, Oleksandr Andrushchenko wrote:
>>>>> --- a/xen/drivers/vpci/header.c
>>>>> +++ b/xen/drivers/vpci/header.c
>>>>> @@ -451,6 +451,32 @@ static void cmd_write(const struct pci_dev *pdev, 
>>>>> unsigned int reg,
>>>>>           pci_conf_write16(pdev->sbdf, reg, cmd);
>>>>>   }
>>>>>   
>>>>> +static void guest_cmd_write(const struct pci_dev *pdev, unsigned int reg,
>>>>> +                            uint32_t cmd, void *data)
>>>>> +{
>>>>> +    /* TODO: Add proper emulation for all bits of the command register. 
>>>>> */
>>>>> +
>>>>> +    if ( (cmd & PCI_COMMAND_INTX_DISABLE) == 0 )
>>>>> +    {
>>>>> +        /*
>>>>> +         * Guest wants to enable INTx. It can't be enabled if:
>>>>> +         *  - host has INTx disabled
>>>>> +         *  - MSI/MSI-X enabled
>>>>> +         */
>>>>> +        if ( pdev->vpci->msi->enabled )
>>>>> +            cmd |= PCI_COMMAND_INTX_DISABLE;
>>>>> +        else
>>>>> +        {
>>>>> +            uint16_t current_cmd = pci_conf_read16(pdev->sbdf, reg);
>>>>> +
>>>>> +            if ( current_cmd & PCI_COMMAND_INTX_DISABLE )
>>>>> +                cmd |= PCI_COMMAND_INTX_DISABLE;
>>>>> +        }
>>>> This last part should be Arm specific. On other architectures we
>>>> likely want the guest to modify INTx disable in order to select the
>>>> interrupt delivery mode for the device.
>>> We cannot allow a guest to clear the bit when it has MSI / MSI-X
>>> enabled - only one of the three is supposed to be active at a time.
>>> (IOW similarly we cannot allow a guest to enable MSI / MSI-X when
>>> the bit is clear.)
>> Sure, but this code is making the bit sticky, by not allowing
>> INTX_DISABLE to be cleared once set. We do not want that behavior on
>> x86, as a guest can decide to use MSI or INTx. The else branch needs
>> to be Arm only.
> Isn't the "else" part questionable even on Arm?
It is. Once fixed I can't see anything Arm specific here
>
> Jan
>

 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.