[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 3/3] AMD/IOMMU: iommu_enable vs iommu_intremap


  • To: Jan Beulich <jbeulich@xxxxxxxx>
  • From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
  • Date: Wed, 3 Nov 2021 18:00:08 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7E24NxF7hiAupysPcbVLz2RmMrpixKrNtgEVV8OTdfA=; b=S8bPM+dmenGnA0JkqpNCzwQ6kz/QcMZ8PIU+mYRMrH30Vqn/26P8cjdQ2UqytcxzsL/Wet6fxaLhc5nRxChj0lrISdyOvTwytTWOsbZ4/zt9+R1Q/2L/pck7+7qQ5EN8VUe6OH1encxgYHNdkEevQVvrvB/Jwm/inmHX4Uw5RUBbbDM8x2LzsUmtahi2VJGEjmUnashytodspuSjs3WDTVDXvPi1Ns/YhvT6cmH1+sNB00CEvwrY5U1d+Ik4ZIjWmFHp8ivuD7c1suGz58QxvR0m7+VxvGULRjWkORgnDHF8cqpDxfOExAHgQ5CHtZCSMATtk5C3hRy7ozJ2pEEhNw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W3Mt3+VFqHVtDR6oeNjrXP2lku7gxIVU6ZAmN+WE1MeeXkfOzYJkfv9AwZoXbM18TH2/t8BtljHa8tEs7UVIibWOGGQ4Z5cJWiClUcrbRuuoZxXh5EuY+MFt8kvfsAh6SjsVlhMxRrSC9P31zfrHuvduQHFJkCJ09xi50gxSZxdanp2E5MUmoix3w3wgz9BhVvHAZaFCkWZZC5Sxzdht1koKZkQTkqSas89lcEsAsWE4gW31rf/DCMmf0T8Ku2xovAENk7l69JiRBuV1wjR+xsY2lL61SkuWzSIfv30zAAoeO82ncMf3pavUfiv2872j7bXAWXv5ZgjvKAJUXfmwWQ==
  • Authentication-results: esa6.hc3370-68.iphmx.com; dkim=pass (signature verified) header.i=@citrix.onmicrosoft.com
  • Cc: Paul Durrant <paul@xxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
  • Delivery-date: Wed, 03 Nov 2021 17:00:31 +0000
  • Ironport-data: A9a23:LiE0iKuLfOEM7z7AFN66qMQ/K+fnVLpZMUV32f8akzHdYApBsoF/q tZmKWiAaPqOZjT1edxzaIzj/BkEuZTdn4NjTVE5+H1gFCoa+JbJXdiXEBz9bniYRiHhoOOLz Cm8hv3odp1coqr0/0/1WlTZQP0VOZigHtIQMsadUsxKbVIiGHhJZS5LwbZj29cx2YPhWGthh PupyyHhEA79s9JLGjp8B5Kr8HuDa9yr5Vv0FnRnDRx6lAe2e0s9VfrzFonoR5fMeaFGH/bSe gr25OrRElU1XfsaIojNfr7TKiXmS1NJVOSEoiI+t6OK2nCuqsGuu0qS2TV1hUp/0l20c95NJ Nplk7O/FT4XOojwluUTajhqSCA9D5dY0eqSSZS/mZT7I0zudnLtx7NlDV0sPJ1e8eFyaY1M3 aVGcnZXNEnF3r/ohuLgIgVvrp1LwM3DJoQQt2sm1TjEJf0nXYrCU+PB4towMDIY254fQqmOO pRxhTxHNxfBQiRmZ3QrLpMQo/eZl0fmVj1VgQfAzUYwyzeKl1EguFT3C/LFd9rPSchLk0Kwo mPd43+/EhwcLMaYyzeO7jSrnOCntTz/cJIfEvu/7PECqF+Zy3EXCRYWfUCmuvT/gUm7M/pHI lEQ0jojq+417kPDczXmd0Tm+jje5EdaAocOVb1hgO2Q9kbKyyC2CTQ9cDpkVNInuvYXd2crl W2zgfq8UFSDr4apYX6a876Vqxa7Ni4UMXIOaEc4cOcV3zXwiNpt10ySF76PBIbw14SoQm+on 1hmuQBn3+1L5fPnwZlX6rwub9iEgpHSBjA46QzMNo5OxlMoPdX1D2BEBLWy0BqhEGp7ZgXe1 JTns5LHhAzrMX1rvHbTKAnqNOv4j8tpyBWG3TZS82AJrlxBAUKLc4FK+y1ZL0x0KMsCcjKBS BaN4l4Bu88NZCH2PfAfj2eN5yICl/aI+TPNDai8UzazSsIpKF/vEN9GPBb4M5/RfLgEzvhkZ MbznTeEBncGE6V3pAdatM9GuYLHMhsWnDuJLbiilkzP+ePHOBa9FOdUWHPTP7tRxP7V/23oH yN3apLiJ+N3C7alPEE6MOc7cDg3EJTMLcuq8JcPJrLYeVcO9aNII6a5/I7NsrdNxsx9vuzJ4 mu8Sglfzl/+jmfAMgKEdjZob7aHYHq1hStT0fUEMQn61n49T5yo6atDJZI7caN+rL5ozOJuT ulDcMKFW6wdRjPC8jUbTJ/8sI09K0j72VPQZ3KoMGolYpptZw3V4du4LAHhwzYDU3isvswkr rz+ig6CGcgfRx5vBdr9Ye60yw/jpmAUne9/BhOaItRadEj23pJtLij90q0+L80WcE2RzTqGz QeGRxwfoLCV8YMy9dDIg4GCrpuoTLQiThYLQTGD4O/vZyfA/2elzYtRa8qyfGjQBDHu5aGvR eRJ1PWgYvcJq0lH7thnGLFxwKNgu9a2/+1Gzh5pFWngZkiwDu8yOWGP2MRCu/EfxrJdvgfqC EuD9sMDZOeMMcLhVlUQOBAkfqKI0vRNwmve6vE8IUPb4i5r/eXYDRUObkfU0CENfqFoNI4Fw Ps6vJ9E4gOyvRMmL9Kag30G7G+LNHEBD/0qu5xy7FUHUeb3JoWuuaDhNxI=
  • Ironport-hdrordr: A9a23:Hu6fJK8W/M1rCx6l5Xtuk+FEdb1zdoMgy1knxilNoENuHPBwxv rAoB1E73PJYVYqOE3Jmbi7Sc+9qFfnhONICO4qTMuftWjdyRGVxeRZjLcKrAeQfhEWmtQtsZ uINpIOd+EYbmIK/foSgjPIa+rIqePvmMvD6Ja8vhUdPj2CKZsQlDuRYjzrY3GeLzM2fKbReq Dsgfau8FGbCAoqh4mAdzQ4dtmGg+eOuIPtYBYACRJiwA6SjQmw4Lq/NxSDxB8RXx5G3L9nqA H+4kPEz5Tml8v+5g7X1mfV4ZgTsNz9yuFbDMjJrsQOMD3jhiuheYwkcbyfuzIepv2p9T8R4Z XxiiZlG/42x2Laf2mzrxeo8w780Aw243un8lOciWuLm72weBsKT+56wa5JeBrQ7EQt+Ptm1r hQ4m6fv51LSTvdgSXU/bHzJlFXv3vxhUBnvf8YjnRZX4dbQqRWt5Yj8ERcF4pFND7m6bogDP JlAKjnlbdrmGuhHjLkV1RUsZmRtixZJGbDfqFCgL3a79FupgE786NCr/Zv2Uvp9/oGOtB5Dq r/Q+JVfYp1P7orhJRGdZE8qPuMex7wqC33QRavyHTcZeo60iH22tTKCItc3pDcRHVP9upqpK j8
  • Ironport-sdr: y5+XZMR1l0qtGF3CL4avDFiiHA9lrHK0o2Ols3lD35qWqlcjV24A7JEwqWAmgYVx9+VUytSGyb jjUwiHDkPvtSnKXX90zeqkgiTDy+AV0btKfdDnlNbRqwMeLHmdJ03CSDNNsWpGfFyds1sqc1/v OAFog/pka4iylPOIb6E6A6GZUTnjRAR8da816M6zdp21qONAMx5rN3gtAAPNx4QePy6eQg8ZOK +wHdzzqmH/wQ2MoG/WZbx+ek5IMafUBnvjTs+FBSoqUCir4RHCXwr/3d7KN/Pn1FDUJSmoxhMz 6rAjXbkDzdfVAGo1+2pRyfx0
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On Wed, Nov 03, 2021 at 04:15:52PM +0100, Jan Beulich wrote:
> On 03.11.2021 16:06, Roger Pau Monné wrote:
> > On Wed, Nov 03, 2021 at 10:46:40AM +0100, Jan Beulich wrote:
> >> On 02.11.2021 12:03, Roger Pau Monné wrote:
> >>> On Tue, Nov 02, 2021 at 11:13:08AM +0100, Jan Beulich wrote:
> >>>> On 25.10.2021 12:28, Roger Pau Monné wrote:
> >>>>> On Thu, Oct 21, 2021 at 11:59:02AM +0200, Jan Beulich wrote:
> >>>>>> The two are really meant to be independent settings; iov_supports_xt()
> >>>>>> using || instead of && was simply wrong. The corrected check is,
> >>>>>> however, redundant, just like the (correct) one in iov_detect(): These
> >>>>>> hook functions are unreachable without acpi_ivrs_init() installing the
> >>>>>> iommu_init_ops pointer, which it does only upon success. (Unlike for
> >>>>>> VT-d there is no late clearing of iommu_enable due to quirks, and any
> >>>>>> possible clearing of iommu_intremap happens only after 
> >>>>>> iov_supports_xt()
> >>>>>> has run.)
> >>>>>>
> >>>>>> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
> >>>>>> ---
> >>>>>> In fact in iov_detect() it could be iommu_enable alone which gets
> >>>>>> checked, but this felt overly aggressive to me. Instead I'm getting the
> >>>>>> impression that the function may wrongly not get called when 
> >>>>>> "iommu=off"
> >>>>>> but interrupt remapping is in use: We'd not get the interrupt handler
> >>>>>> installed, and hence interrupt remapping related events would never get
> >>>>>> reported. (Same on VT-d, FTAOD.)
> >>>>>
> >>>>> I've spend a non-trivial amount of time looking into this before
> >>>>> reading this note. AFAICT you could set iommu=off and still get x2APIC
> >>>>> enabled and relying on interrupt remapping.
> >>>>
> >>>> Right, contrary to ...
> >>>>
> >>>>>> For iov_supports_xt() the question is whether, like VT-d's
> >>>>>> intel_iommu_supports_eim(), it shouldn't rather check iommu_intremap
> >>>>>> alone (in which case it would need to remain a check rather than 
> >>>>>> getting
> >>>>>> converted to ASSERT()).
> >>>>>
> >>>>> Hm, no, I don't think so. I think iommu_enable should take precedence
> >>>>> over iommu_intremap, and having iommu_enable == false should force
> >>>>> interrupt remapping to be reported as disabled. Note that disabling it
> >>>>> in iommu_setup is too late, as the APIC initialization will have
> >>>>> already taken place.
> >>>>>
> >>>>> It's my reading of the command line parameter documentation that
> >>>>> setting iommu=off should disable all usage of the IOMMU, and that
> >>>>> includes the interrupt remapping support (ie: a user should not need
> >>>>> to set iommu=off,no-intremap)
> >>>>
> >>>> ... that documentation. But I think it's the documentation that
> >>>> wants fixing, such that iommu=off really only control DMA remap.
> >>>
> >>> IMO I think it's confusing to have sub-options that could be enabled
> >>> when you set the global one to off. I would expect `iommu=off` to
> >>> disable all the iommu related options, and I think it's fair for
> >>> people to expect that behavior.
> >>
> >> It occurs to me that this reply of yours here contradicts your R-b
> >> on patch 1, in particular with its revision log saying:
> >>
> >> v2: Treat iommu_enable and iommu_intremap as separate options.
> > 
> > Right, I see. patch 1 uses
> > 
> > if ( !iommu_enable && !iommu_intremap )
> >     return;
> > 
> > Which I think should be:
> > 
> > if ( !iommu_enable )
> >     return;
> > 
> > Sorry I didn't realize in that context. I think we need to decide
> > whether we want to fix the documentation to match the code, or whether
> > we should fix the code to match the documentation.
> 
> Except that adjusting the conditional(s) in patch 1 would then
> be a functional change that's not really the purpose of that
> patch - it really only folds acpi_ivrs_init()'s and
> acpi_parse_dmar()'s into a vendor-independent instance in
> acpi_iommu_init().

Right.

> Alternatively we could adjust the conditional
> here (in patch 3), but that would feel unrelated once again, as
> this change is supposed to be AMD-specific.

Depending on what we end up doing regarding interrupt remapping being
disabled with iommu=off we might want to rework patch 3.

> > My preference would be for the latter, because I think the resulting
> > interface would be clearer. That will require introducing a new
> > dmaremap iommu suboption, but again I think this will result in a
> > better interface overall.
> 
> I guess we could do with a 3rd opinion: Paul, any chance?
> 
> In any event I hope that we can agree that patches 1 and 2 are
> okay for 4.16 in their present shape, and patch 3 (plus whichever
> further ones) would better wait for post-4.16?

I consider the issues either a bug in the documentation or the code,
so it's likely I would suggest whatever fix we end up doing to be
backported. At which point it might make sense to add to the release.

I don't think it should be a blocked though, as this hasn't been
introduced in this release.

Thanks, Roger.



 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.