Re: [PATCH v11 3/3] xen/arm64: io: Handle data abort due to cache maintenance instructions

[Julien Grall <julien@xxxxxxx>]

Hi,

On 22/03/2022 16:16, Ayan Kumar Halder wrote:
> On 22/03/2022 13:22, Julien Grall wrote:
> > Furthermore, I think try_fwd_ioserv() need to be adapted because the 
> > function will use the fields SAS and SRT. From the Arm Arm they are 
> > RES0, so while they are 0 today, we should not rely on this.
> > Therefore, to be fully compliant with the Arm, we want to reorder a 
> > bit the code:
> >  * The field data could be set past ioreq_select_server().
> >  * The field size should be set to the cache line size.
> I am assuming that we need to invoke  dcache_line_size() (from 
> xen/arch/arm/arm64/cache.S ) to get the cache line size.
You would want to use dcache_line_bytes.

> I think the cache line may be 32 or 64 bytes. In which case, this cannot 
> be represented by SAS (as it can represent 1, 2, 4 and 8 bytes).
You are correct that this cannot be represented by SAS. However, I was 
referring to the field 'size' in the ioreq structure. It is a 32-bit 
integer and could therefore represent the size of the cache line.
> Also, we are invoking ioreq_select_server() to determine if the address 
> is emulated or not. So, can we use an assumed size (= 1 byte) ?
I thought about this. This is technically incorrect but would be OK if 
we cannot find the correct size.
Per above, I think the correct size could be found.

Cheers,

--
Julien Grall