[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH V5 1/2] xen/arm: Add i.MX lpuart driver
Hi Peng, > On 14 Apr 2022, at 08:44, Peng Fan (OSS) <peng.fan@xxxxxxxxxxx> wrote: > > From: Peng Fan <peng.fan@xxxxxxx> > > The i.MX LPUART Documentation: > https://www.nxp.com/webapp/Download?colCode=IMX8QMIEC > Chatper 13.6 Low Power Universal Asynchronous Receiver/ > Transmitter (LPUART) > > Tested-by: Henry Wang <Henry.Wang@xxxxxxx> > Signed-off-by: Peng Fan <peng.fan@xxxxxxx> Asked-by: Bertrand Marquis <bertrand.marquis@xxxxxxx> I did not check the code but enough people went through this so I think it can be merged. Cheers Bertrand > --- > xen/arch/arm/include/asm/imx-lpuart.h | 64 ++++++ > xen/drivers/char/Kconfig | 7 + > xen/drivers/char/Makefile | 1 + > xen/drivers/char/imx-lpuart.c | 276 ++++++++++++++++++++++++++ > 4 files changed, 348 insertions(+) > create mode 100644 xen/arch/arm/include/asm/imx-lpuart.h > create mode 100644 xen/drivers/char/imx-lpuart.c > > diff --git a/xen/arch/arm/include/asm/imx-lpuart.h > b/xen/arch/arm/include/asm/imx-lpuart.h > new file mode 100644 > index 0000000000..fe859045dc > --- /dev/null > +++ b/xen/arch/arm/include/asm/imx-lpuart.h > @@ -0,0 +1,64 @@ > +/* > + * xen/arch/arm/include/asm/imx-lpuart.h > + * > + * Common constant definition between early printk and the LPUART driver > + * > + * Peng Fan <peng.fan@xxxxxxx> > + * Copyright 2022 NXP > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#ifndef __ASM_ARM_IMX_LPUART_H__ > +#define __ASM_ARM_IMX_LPUART_H__ > + > +/* 32-bit register definition */ > +#define UARTBAUD (0x10) > +#define UARTSTAT (0x14) > +#define UARTCTRL (0x18) > +#define UARTDATA (0x1C) > +#define UARTMATCH (0x20) > +#define UARTMODIR (0x24) > +#define UARTFIFO (0x28) > +#define UARTWATER (0x2c) > + > +#define UARTSTAT_TDRE BIT(23, UL) > +#define UARTSTAT_TC BIT(22, UL) > +#define UARTSTAT_RDRF BIT(21, UL) > +#define UARTSTAT_OR BIT(19, UL) > + > +#define UARTBAUD_OSR_SHIFT (24) > +#define UARTBAUD_OSR_MASK (0x1f) > +#define UARTBAUD_SBR_MASK (0x1fff) > +#define UARTBAUD_BOTHEDGE (0x00020000) > +#define UARTBAUD_TDMAE (0x00800000) > +#define UARTBAUD_RDMAE (0x00200000) > + > +#define UARTCTRL_TIE BIT(23, UL) > +#define UARTCTRL_TCIE BIT(22, UL) > +#define UARTCTRL_RIE BIT(21, UL) > +#define UARTCTRL_ILIE BIT(20, UL) > +#define UARTCTRL_TE BIT(19, UL) > +#define UARTCTRL_RE BIT(18, UL) > +#define UARTCTRL_M BIT(4, UL) > + > +#define UARTWATER_RXCNT_OFF 24 > + > +#endif /* __ASM_ARM_IMX_LPUART_H__ */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig > index 2ff5b288e2..e5f7b1d8eb 100644 > --- a/xen/drivers/char/Kconfig > +++ b/xen/drivers/char/Kconfig > @@ -13,6 +13,13 @@ config HAS_CADENCE_UART > This selects the Xilinx Zynq Cadence UART. If you have a Xilinx Zynq > based board, say Y. > > +config HAS_IMX_LPUART > + bool "i.MX LPUART driver" > + default y > + depends on ARM_64 > + help > + This selects the i.MX LPUART. If you have i.MX8QM based board, say Y. > + > config HAS_MVEBU > bool "Marvell MVEBU UART driver" > default y > diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile > index 7c646d771c..14e67cf072 100644 > --- a/xen/drivers/char/Makefile > +++ b/xen/drivers/char/Makefile > @@ -8,6 +8,7 @@ obj-$(CONFIG_HAS_MVEBU) += mvebu-uart.o > obj-$(CONFIG_HAS_OMAP) += omap-uart.o > obj-$(CONFIG_HAS_SCIF) += scif-uart.o > obj-$(CONFIG_HAS_EHCI) += ehci-dbgp.o > +obj-$(CONFIG_HAS_IMX_LPUART) += imx-lpuart.o > obj-$(CONFIG_ARM) += arm-uart.o > obj-y += serial.o > obj-$(CONFIG_XEN_GUEST) += xen_pv_console.o > diff --git a/xen/drivers/char/imx-lpuart.c b/xen/drivers/char/imx-lpuart.c > new file mode 100644 > index 0000000000..df44f91e5d > --- /dev/null > +++ b/xen/drivers/char/imx-lpuart.c > @@ -0,0 +1,276 @@ > +/* > + * xen/drivers/char/imx-lpuart.c > + * > + * Driver for i.MX LPUART. > + * > + * Peng Fan <peng.fan@xxxxxxx> > + * Copyright 2022 NXP > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <xen/errno.h> > +#include <xen/init.h> > +#include <xen/irq.h> > +#include <xen/mm.h> > +#include <xen/serial.h> > +#include <asm/device.h> > +#include <asm/imx-lpuart.h> > +#include <asm/io.h> > + > +#define imx_lpuart_read(uart, off) readl((uart)->regs + off) > +#define imx_lpuart_write(uart, off, val) writel((val), (uart)->regs + off) > + > +static struct imx_lpuart { > + uint32_t baud, clock_hz, data_bits, parity, stop_bits, fifo_size; > + uint32_t irq; > + char __iomem *regs; > + struct irqaction irqaction; > + struct vuart_info vuart; > +} imx8_com; > + > +static void imx_lpuart_interrupt(int irq, void *data, > + struct cpu_user_regs *regs) > +{ > + struct serial_port *port = data; > + struct imx_lpuart *uart = port->uart; > + uint32_t sts, rxcnt; > + > + sts = imx_lpuart_read(uart, UARTSTAT); > + rxcnt = imx_lpuart_read(uart, UARTWATER) >> UARTWATER_RXCNT_OFF; > + > + if ( (sts & UARTSTAT_RDRF) || (rxcnt > 0) ) > + serial_rx_interrupt(port, regs); > + > + if ( sts & UARTSTAT_TDRE ) > + serial_tx_interrupt(port, regs); > + > + imx_lpuart_write(uart, UARTSTAT, sts); > +} > + > +static void __init imx_lpuart_init_preirq(struct serial_port *port) > +{ > + struct imx_lpuart *uart = port->uart; > + uint32_t ctrl, old_ctrl, bd; > + > + old_ctrl = imx_lpuart_read(uart, UARTCTRL); > + ctrl = (old_ctrl & ~UARTCTRL_M) | UARTCTRL_TE | UARTCTRL_RE; > + bd = imx_lpuart_read(uart, UARTBAUD); > + > + while ( !(imx_lpuart_read(uart, UARTSTAT) & UARTSTAT_TC) ) > + cpu_relax(); > + > + /* Disable transmit and receive */ > + imx_lpuart_write(uart, UARTCTRL, old_ctrl & ~(UARTCTRL_TE | > UARTCTRL_RE)); > + > + /* Reuse firmware baudrate settings, only disable DMA here */ > + bd &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); > + > + imx_lpuart_write(uart, UARTMODIR, 0); > + imx_lpuart_write(uart, UARTBAUD, bd); > + imx_lpuart_write(uart, UARTCTRL, ctrl); > +} > + > +static void __init imx_lpuart_init_postirq(struct serial_port *port) > +{ > + struct imx_lpuart *uart = port->uart; > + uint32_t temp; > + > + uart->irqaction.handler = imx_lpuart_interrupt; > + uart->irqaction.name = "imx_lpuart"; > + uart->irqaction.dev_id = port; > + > + if ( setup_irq(uart->irq, 0, &uart->irqaction) != 0 ) > + { > + dprintk(XENLOG_ERR, "Failed to allocate imx_lpuart IRQ %d\n", > + uart->irq); > + return; > + } > + > + /* Enable interrupts */ > + temp = imx_lpuart_read(uart, UARTCTRL); > + temp |= (UARTCTRL_RIE | UARTCTRL_TIE); > + temp |= UARTCTRL_ILIE; > + imx_lpuart_write(uart, UARTCTRL, temp); > +} > + > +static void imx_lpuart_suspend(struct serial_port *port) > +{ > + BUG(); > +} > + > +static void imx_lpuart_resume(struct serial_port *port) > +{ > + BUG(); > +} > + > +static int imx_lpuart_tx_ready(struct serial_port *port) > +{ > + struct imx_lpuart *uart = port->uart; > + > + return imx_lpuart_read(uart, UARTSTAT) & UARTSTAT_TC; > +} > + > +static void imx_lpuart_putc(struct serial_port *port, char c) > +{ > + struct imx_lpuart *uart = port->uart; > + > + while ( !(imx_lpuart_read(uart, UARTSTAT) & UARTSTAT_TDRE) ) > + cpu_relax(); > + > + imx_lpuart_write(uart, UARTDATA, c); > +} > + > +static int imx_lpuart_getc(struct serial_port *port, char *pc) > +{ > + struct imx_lpuart *uart = port->uart; > + int ch; > + > + while ( !(imx_lpuart_read(uart, UARTSTAT) & UARTSTAT_RDRF) ) > + return 0; > + > + ch = imx_lpuart_read(uart, UARTDATA); > + *pc = ch & 0xff; > + > + if ( imx_lpuart_read(uart, UARTSTAT) & UARTSTAT_OR ) > + imx_lpuart_write(uart, UARTSTAT, UARTSTAT_OR); > + > + return 1; > +} > + > +static int __init imx_lpuart_irq(struct serial_port *port) > +{ > + struct imx_lpuart *uart = port->uart; > + > + return ((uart->irq > 0) ? uart->irq : -1); > +} > + > +static const struct vuart_info *imx_lpuart_vuart_info(struct serial_port > *port) > +{ > + struct imx_lpuart *uart = port->uart; > + > + return &uart->vuart; > +} > + > +static void imx_lpuart_start_tx(struct serial_port *port) > +{ > + struct imx_lpuart *uart = port->uart; > + uint32_t temp; > + > + temp = imx_lpuart_read(uart, UARTSTAT); > + /* Wait until empty */ > + while ( !(temp & UARTSTAT_TDRE) ) > + cpu_relax(); > + > + temp = imx_lpuart_read(uart, UARTCTRL); > + imx_lpuart_write(uart, UARTCTRL, (temp | UARTCTRL_TIE)); > +} > + > +static void imx_lpuart_stop_tx(struct serial_port *port) > +{ > + struct imx_lpuart *uart = port->uart; > + uint32_t temp; > + > + temp = imx_lpuart_read(uart, UARTCTRL); > + temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); > + imx_lpuart_write(uart, UARTCTRL, temp); > +} > + > +static struct uart_driver __read_mostly imx_lpuart_driver = { > + .init_preirq = imx_lpuart_init_preirq, > + .init_postirq = imx_lpuart_init_postirq, > + .endboot = NULL, > + .suspend = imx_lpuart_suspend, > + .resume = imx_lpuart_resume, > + .tx_ready = imx_lpuart_tx_ready, > + .putc = imx_lpuart_putc, > + .getc = imx_lpuart_getc, > + .irq = imx_lpuart_irq, > + .start_tx = imx_lpuart_start_tx, > + .stop_tx = imx_lpuart_stop_tx, > + .vuart_info = imx_lpuart_vuart_info, > +}; > + > +static int __init imx_lpuart_init(struct dt_device_node *dev, > + const void *data) > +{ > + const char *config = data; > + struct imx_lpuart *uart; > + int res; > + u64 addr, size; > + > + if ( strcmp(config, "") ) > + printk("WARNING: UART configuration is not supported\n"); > + > + uart = &imx8_com; > + > + uart->baud = 115200; > + uart->data_bits = 8; > + uart->parity = 0; > + uart->stop_bits = 1; > + > + res = dt_device_get_address(dev, 0, &addr, &size); > + if ( res ) > + { > + printk("imx8-lpuart: Unable to retrieve the base" > + " address of the UART\n"); > + return res; > + } > + > + res = platform_get_irq(dev, 0); > + if ( res < 0 ) > + { > + printk("imx8-lpuart: Unable to retrieve the IRQ\n"); > + return -EINVAL; > + } > + uart->irq = res; > + > + uart->regs = ioremap_nocache(addr, size); > + if ( !uart->regs ) > + { > + printk("imx8-lpuart: Unable to map the UART memory\n"); > + return -ENOMEM; > + } > + > + uart->vuart.base_addr = addr; > + uart->vuart.size = size; > + uart->vuart.data_off = UARTDATA; > + /* tmp from uboot */ > + uart->vuart.status_off = UARTSTAT; > + uart->vuart.status = UARTSTAT_TDRE; > + > + /* Register with generic serial driver */ > + serial_register_uart(SERHND_DTUART, &imx_lpuart_driver, uart); > + > + dt_device_set_used_by(dev, DOMID_XEN); > + > + return 0; > +} > + > +static const struct dt_device_match imx_lpuart_dt_compat[] __initconst = > +{ > + DT_MATCH_COMPATIBLE("fsl,imx8qm-lpuart"), > + { /* sentinel */ }, > +}; > + > +DT_DEVICE_START(imx_lpuart, "i.MX LPUART", DEVICE_SERIAL) > + .dt_match = imx_lpuart_dt_compat, > + .init = imx_lpuart_init, > +DT_DEVICE_END > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > -- > 2.35.1 >
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