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Re: [PATCH] x86/msr: handle reads to MSR_P5_MC_ADDR
- To: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Thu, 28 Apr 2022 09:55:33 +0200
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Steffen Einsle <einsle@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Thu, 28 Apr 2022 07:55:42 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 27.04.2022 17:47, Roger Pau Monne wrote:
> I've added it for CENTAUR and SHANGHAI because the MSR is there since
> Pentium, so likely to be implemented by those vendors also, but have
> no way to check.
I think that's fine.
> I wonder how long it will take for Windows to also start poking at
> MSR_IA32_MC0_ADDR or other MCE related registers. For now this seems
> to be enough.
Those are handled by vmce_{rd,wr}msr(), aren't they? As a result I
wonder whether the MSR in question as well as its companion
P5_MC_TYPE wouldn't better also be handled (faked) there. (Even if
not, I don't think we should handle ADDR by not TYPE.)
Jan
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