[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2] x86/msr: handle reads to MSR_P5_MC_{ADDR,TYPE}
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Thu, 28 Apr 2022 12:52:50 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LX8f38mpLEajZFN110opSJeEK9TsOBhL4snGced19tU=; b=U+Z55g9Dq7AK/VNftslW/g/UnQy2FIaLXqrLU2pVH57fS5sk2spYre4MDiUilqKv1BFbTf20SVlOJ4mHrL3/DJYkpLAyYYcjIlTFJai9I+WwbjfyW/n/BTOXqk06Dn95zGsSIofpBrfpHlC8/9fEtBkNtXLHvqF8vVHDEQ2VadWw20C4Bfa/egbdshIq0OdCY/zfu7cXREx+BG1v4143E/0VkEMNVfgstXgDvF5D/oLhkwcESVL49AwY9OuSfc+ejfEoNV+qfpj4NNbhLkzG4U7oxzVp2Bx0eujiwGlmPX/1qSTYjzZ+zL35mVYUDnwIrKUyH+afvIG2/j5H8RxXWA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lEQAkElepIYxpTRyVDqC5/qbBdBXHLZHgjVkHWBd+891ocxeTGeQyG01ZGp88VzAHsWTH8a5z1I+ZC5K4gzePNFoejkmc7F2g1jarQm/1l/SDA444ORyg2Vx7Qnp91hljLZWNKZsv98NDFtye7olvBmRCoZdw3q2joG23sHiV3IXA9nx79VNFRtCnmzKVfPvF+0c3tvy5KXsCb8Uu84zrcExYOkH9WaYjSuSVcx06b+w6VBUNBgjtrtgjnrJUM2AL9wOloWODn6BicVAxi/muBqnUDgEMF46ZYE44vBu9BhUHrDrh+PiRRaTYmsYnS+gQrm5/VlosXA5uJ5gsjoAWA==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Steffen Einsle <einsle@xxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Thu, 28 Apr 2022 10:53:22 +0000
- Ironport-data: A9a23:MPRQaqhXKkHs+T+ZrDbZNfhEX161YREKZh0ujC45NGQN5FlHY01je htvW26GO6yOMTH1c9B0OYqz9EgDuJTUmtRmTQZr/yljE3wb9cadCdqndUqhZCn6wu8v7a5EA 2fyTvGacajYm1eF/k/F3oDJ9CU6jefSLlbFILas1hpZHGeIcw98z0M78wIFqtQw24LhX1nd4 YqaT/D3YzdJ5RYlagr41IrbwP9flKyaVOQw5wFWiVhj5TcyplFNZH4tDfjZw0jQG+G4KtWSV efbpIxVy0uCl/sb5nFJpZ6gGqECaua60QFjERO6UYD66vRJjnRaPqrWqJPwwKqY4tmEt4kZ9 TlDiXC/YVw2BpbFx91aahtJVCEiJK5Ev+DsYlHq5KR/z2WeG5ft69NHKRhseKc+qqNwC2wI8 uEEIjcQaBzFn/ix3L+wVuhrgIIkMdXvO4Qc/HpnyFk1D95/GcyFH/qMuIIehWht7ixNNa+2i 84xcz1gYQ6GexRSElwWFIg/jKGjgXyXnzhw9wrI/vNmuzS7IApZ0aDEFsuMQdmzBtRJx32dl FOYzVTnDURPXDCY4X/fmp62vcfNly7mXIMZFJWj6+VnxlaUwwQ7Fxk+RVa95/6jhSaWVtNZM EgZ0jIutbQo9VztQtSVdw21pjuIswARX/JUEvYm80edx6zM+QGbC2MYCDlbZ7QbWNQeQDUr0 hqDmYPvDDk26rmNEyvCq/GTsC+4PjUTISkafygYQAAZ4t7l5oYukhbISdUlG6mw5jHoJQzNL /mxhHBWr90uYQQjjs1XIXivb+qQm6X0
- Ironport-hdrordr: A9a23:IFQ0X6zWZWu/fORnXdZ/KrPxsOskLtp133Aq2lEZdPULSKGlfp GV9sjziyWetN9wYh4dcB67Scy9qFfnhOZICOgqTM6ftWzd1FdAQ7sD0WKP+UyCJ8S6zJ8n6U 4CSdkDNDSTNykcsS+S2mDRfbcdKZu8gcaVbI/lvgpQpGpRGsVdBmlCe2Sm+hocfng9OXN1Lu vr2uN34x6bPVgHZMWyAXcIG8DFut3wjZrjJToLHQQu5gWihS6hrOeSKWnR4j4uFxd0hZsy+2 nMlAL0oo2lrvGA0xfZk0ve9Y5fltfNwsZKQOaMls8WADPxjRvAXvUpZ5Sy+BQO5M2/4lcjl9 fB5z8mIsRI8nvUOlq4pBP8sjOQpQoG2jvH8xu1kHHjqcv2SHYREMxan79UdRPf9g4JoMx8+L gj5RPUi7NnSTf72Ajt7dnBUB9n0mCup2A5rOIVh3tDFaMDdb5qq5AF9k89KuZMIMvD0vFoLA BSNrCc2B4PGmnqL0wx/1MfiuBEZ05DUStvGSM5y4+oOzs/pgEK86JX/r1cop46zuNCd3B13Z W6Dk1WrsA+ciY3V9MIOA5Te7rBNoTyKSi8QF66EBDAKJwtHU7rhtre3IgVjdvaC6DgiqFC06 j8bA==
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Thu, Apr 28, 2022 at 12:39:19PM +0200, Jan Beulich wrote:
> On 28.04.2022 11:13, Roger Pau Monne wrote:
> > --- a/xen/arch/x86/cpu/mcheck/mce_intel.c
> > +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
> > @@ -1008,8 +1008,24 @@ int vmce_intel_wrmsr(struct vcpu *v, uint32_t msr,
> > uint64_t val)
> >
> > int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val)
> > {
> > + const struct cpuid_policy *cp = v->domain->arch.cpuid;
> > unsigned int bank = msr - MSR_IA32_MC0_CTL2;
> >
> > + switch ( msr )
> > + {
> > + case MSR_P5_MC_ADDR:
> > + /* Bank 0 is used for the 'bank 0 quirk' on older processors. */
> > + *val = v->arch.vmce.bank[1].mci_addr;
> > + return 1;
> > +
> > + case MSR_P5_MC_TYPE:
> > + *val = v->arch.vmce.bank[1].mci_status;
> > + return 1;
> > + }
>
> Could I ask you to add a reference to vcpu_fill_mc_msrs() in the comment?
Sure.
Thanks, Roger.
|
