[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 0/3] amd/msr: implement MSR_VIRT_SPEC_CTRL for HVM guests
- To: xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Roger Pau Monne <roger.pau@xxxxxxxxxx>
- Date: Tue, 3 May 2022 10:26:47 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=O3qHloybC+YWjO8T943bJ2MyrTbnzE0pNcV0UG+PM68=; b=T4MJV43XM34Uw96xDRGF6akeABjd40ye5UptfBClA9ui0GfwvKmzRZ0Nbx0sOJR3e2j8W4CYGFNScigkwNyRqUbCuE2s6rIi1Kl6O4Y9RR8jeElm1kTwZ/cIZlrcsJsFx0y51u0S/fjfZbZJVuVRmkZmCuUC+hgOiY6FWZEsHjZMgSXgTAj2us80frYRLrQB1vJeBumjgPsvpOnzROqLtKFmf0f8Y1ciFs67KR5lVcZHLaUdC9L8XjyEHvQi3GI8CcSc6fbLHiJq8G/8ksbeJaPERFXm75/8zjf1nCoVEsZtbcvNXob0FshsJI/0tAIasUhCfxseDJ/p9p6WuvWFcg==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=M5AT45Y4Xrp+uFyV9z3ycycOsZPUZIdXmZCv7KJ+yEeY8sr+XVpWQPKMoJZg48o7/qxfsjxzOG3VHf5vj0rLuTaeg+dTrjTmYm3274pFqi/1oBNTGSNBTQoL3ONEAM/vRIi/aIibe84EJldUnVls+xpdn8NANAzgkpDOzgbKATG7GfCyJm6osEbHB6NvK1f/IXNtlhb4pCXy1FP6GtaxPQNCEOUK0Qk0oBqMv/s1ehWCm+C3f5A6wVIuCAGo35kozAy8GIvF6jbIBQU63nNvaLl0SA2nGdRJd+dLFKbn31Ur6dIwMMGv+M6slER75lDAHGncwSRMQy4EMGsJHSrfwg==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Roger Pau Monne <roger.pau@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Henry Wang <Henry.Wang@xxxxxxx>, Community Manager <community.manager@xxxxxxxxxxxxxx>
- Delivery-date: Tue, 03 May 2022 08:35:16 +0000
- Ironport-data: A9a23:LIxvYaLHB9g7xrJIFE+R8pQlxSXFcZb7ZxGr2PjKsXjdYENSgT0Om GceWDqBPvqPY2H2cop/Ptu2p04Eu5PVm95kGVBlqX01Q3x08seUXt7xwmUcns+xwm8vaGo9s q3yv/GZdJhcokf0/0vrav67xZVF/fngqoDUUYYoAQgsA149IMsdoUg7wbRh39Yz2YHR7z6l4 rseneWOYDdJ5BYsWo4kw/rrRMRH5amaVJsw5zTSVNgT1LPsvyB94KE3fMldG0DQUIhMdtNWc s6YpF2PEsE1yD92Yj+tuu6TnkTn2dc+NyDW4pZdc/DKbhSvOkXee0v0XRYRQR4/ttmHozx+4 Nxu67Dsdz0HB6fdpeUUTBlFTB9uE6ITrdcrIVDn2SCS52vvViO2ht9IVQQxN4Be/ftrC2ZT8 /BeMCoKch2Im+OxxvS8V/VogcMgasLsOevzuFk5lW2fUalgHMmFH/miCdxwhV/cguhUGvnTf YwBYCdHZxXceRxffFwQDfrSmc/33iWjLGAD8zp5o4INyTaKlT16yIL0H4vRRIemZZ0El2yH8 zeuE2PRR0ty2Mak4SqI9Degi/HCmQv/WZkOD/uo+/hymlqRy2cPThoMWjOTo/O0l0q/UNJ3M FEP92wlqq1a3FOvZsnwWVu/unHslj4RXcBBVdIz7g6lw7DRpQ2eAwAsRTlEbcEgtdMnAzkj0 FaGksnBFTFpqKeSS3+W6vGTtzzaBMQOBWoLZCtBRw1c5dDm+N43lkiXEoolF7OphNroHz222 yqNsCU1m7QUi4gMyrm/+lfExTmro/AlUzII2+keZUr9hisRWWJvT9bABYTzhRqYELukcw==
- Ironport-hdrordr: A9a23:uOfNkqMf4fmPkMBcTyf155DYdb4zR+YMi2TDiHoddfUFSKalfp 6V98jztSWatN/eYgBDpTnmAtj5fZq8z+8N3WB1B9uftWbdyQ+Vxe1ZjbcKoAeQZhEWiNQtsp uIGpIWYLOQMbETt7eB3ODSKadE/DDoytHKuQ+IpE0dNj2CJpsQmDtRO0K+KAlbVQNGDZ02GN 614ddGnSOpfTAyYt6gDncIcuDfr5mT/aiWKCIuNloC0k2jnDmo4Ln1H1yx2QofaSpGxfMH/X LemwL0y62/u7WQywPa1UXU85NK8eGRvOdrNYipsIw4Oz/sggGnaMBIXKCDhik8pKWV5FMjgL D30mUdFvU2z0mUUnC+oBPr1QWl+i0p8WXexViRhmamidDlRRohYvAxyL5xQ1/80Q4Nrdt82K VE0yayrJxMFy7Nmyz7+pzhSwxqrEypunAv+NRjxUC3abFuJ4O5kLZvsn+8SPw7bWPHAcEcYa JT5fjnlbprmQjwVQGYgoFtqObcLUjbUC32AXTqgfblrAS+rEoJs3fw+/Zv4EvojKhNLaWsx9 60R5iAx4s+OvP/U8pGdZY8aPryLFDxajTxF0/XCWjbNcg8SgLwQtjMkf0I2N0=
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Hello,
The following series implements support for MSR_VIRT_SPEC_CTRL
(VIRT_SSBD) on different AMD CPU families.
Note that the support is added backwards, starting with the newer CPUs
that support MSR_SPEC_CTRL and moving to the older ones either using
MSR_VIRT_SPEC_CTRL or the SSBD bit in LS_CFG.
Xen is still free to use it's own SSBD setting, as the selection is
context switched on vm{entry,exit}.
On Zen2 and later, SPEC_CTRL.SSBD should exist and should be used in
preference to VIRT_SPEC_CTRL.SSBD. However, for migration
compatibility, Xen offers VIRT_SSBD to guests (in the max cpuid policy,
not default) implemented in terms of SPEC_CTRL.SSBD.
On Fam15h thru Zen1, Xen exposes VIRT_SSBD to guests by default to
abstract away the model and/or hypervisor specific differences in
MSR_LS_CFG/MSR_VIRT_SPEC_CTRL.
So the implementation of VIRT_SSBD exposed to HVM guests will use one of
the following underlying mechanisms, in the preference order listed
below:
* SPEC_CTRL.SSBD: patch 1
* VIRT_SPEC_CTRL.SSBD: patch 2.
* Non-architectural way using LS_CFG: patch 3.
NB: patch 3 introduces some logic in GIF=0 context, such logic has been
kept to a minimum due to the special context it's running on.
Roger Pau Monne (3):
amd/msr: implement VIRT_SPEC_CTRL for HVM guests on top of SPEC_CTRL
amd/msr: allow passthrough of VIRT_SPEC_CTRL for HVM guests
amd/msr: implement VIRT_SPEC_CTRL for HVM guests using legacy SSBD
CHANGELOG.md | 3 +
xen/arch/x86/cpu/amd.c | 121 +++++++++++++++++---
xen/arch/x86/cpuid.c | 17 +++
xen/arch/x86/hvm/hvm.c | 1 +
xen/arch/x86/hvm/svm/entry.S | 8 ++
xen/arch/x86/hvm/svm/svm.c | 39 +++++++
xen/arch/x86/include/asm/amd.h | 4 +
xen/arch/x86/include/asm/cpufeatures.h | 1 +
xen/arch/x86/include/asm/msr.h | 14 +++
xen/arch/x86/msr.c | 26 +++++
xen/arch/x86/spec_ctrl.c | 12 +-
xen/include/public/arch-x86/cpufeatureset.h | 2 +-
12 files changed, 229 insertions(+), 19 deletions(-)
--
2.35.1
|
