[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi
- To: Marek Marczykowski-Górecki <marmarek@xxxxxxxxxxxxxxxxxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Wed, 11 May 2022 09:57:20 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Z5YG+5H5TaKV9mgCpKNyDoJBKbSuy8KSHr32Ip4JaUY=; b=AZx72kLxFmAtE5uZj/an6liFvV1y7++D1JMGniqU0MN94s/wqfGRro+lk5mhlV1Uqy5gNNI8jv/h0e9+CgP3cguBClv75jXI2ZIIjtulRY/buV/XqzVobFYBDKtepKQt/KXUvVZmwSkD5FBuneqdphmLBNiFcw3pXllTo1kmuW029sxXIgjJJYPx9cRaQ9+vjEy/serJqzUbXgHI2gxgeHthxFO+VYC0GpOXlPywVPZ0hg72104bZjzGwyZafq4X31tqzWTdSyJvLg16dUEID3QJkLtcAu/4xERCiqbGkvol8jbCZ32jjlFghC6Z0gdT/0UJ8N7aHxtHsDRt+eHEJw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hrZlElgn/EkNFMbf8vb+di4+gPPDLgBfc47Gxgdk8AVJtZmk124KA7XFkIF/mEJ4tUHVN6eROPj+sSWN7k+iJRbpi4e87uPeRf5u9gQ4nTZxT5hbZ5NyqBEG133fg355mI6JOO8o6QYszAo/8zqjN5c6o7lbufozAdy0/3QdTZc17g8+QGunq7yWPJuICfjzY4cRWg+NCHVOqFtqmJY/tRK3CDGSkO86gwD2NKUZWwUcS+3RYO4ApXpUSZ576Y+pnoRdUe6A3A29MmSzsfFJyjiEMpjIo2J5JYPaKrezz01wijKU5QX4LITtP+2b/kPJZ26mRa4KUt5Bf9u11alFFQ==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, George Dunlap <george.dunlap@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Julien Grall <julien@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Wed, 11 May 2022 07:57:34 +0000
- Ironport-data: A9a23:4cGJba/elmktc3h+qz/mDrUDvH+TJUtcMsCJ2f8bNWPcYEJGY0x3y jdLXWnSOPmMYjP2fdggb46yoRkO7cDXzYUyGQNsrnw8E34SpcT7XtnIdU2Y0wF+jyHgoOCLy +1EN7Es+ehtFie0Si+Fa+Sn9T8mvU2xbuKU5NTsY0idfic5DnZ44f5fs7Rh2NQw3IHgW1rlV e7a+KUzBnf0g1aYDUpMg06zgEsHUCPa4W5wUvQWPJinjXeG/5UnJMt3yZKZdhMUdrJ8DO+iL 9sv+Znilo/vE7XBPfv++lrzWhVirrc/pmFigFIOM0SpqkAqSiDfTs/XnRfTAKtao2zhojx/9 DlCncHtQxwsOqKWpLkYYxpXOSVyHbB/+bCSdBBTseTLp6HHW13F5qw0SWQJZ8gf8OsxBnxS/ /sFLjxLdgqEm++93LO8TK9rm9gnK87oeogYvxmMzxmAVapgHc+FHfuMuYYwMDQY36iiGd7EY MUUc3x3ZQnoaBxTIFYHTpk5mY9Eg1GgKGAE8A7M/8Lb5UDQ41dh3p7RFOaFa8C3TuhLnmeSv yXZqjGR7hYycYb3JSC+2nelnOrGhy74cIMUCryj9/RujUGTx2ocExkfXx2wpvzRol6zXZdTJ lIZ/gIqrLMu7wq7Q9/lRRq6rXWY+BkGVLJ4Eec39QWMwar8+BuCCy4PSTspQN47sM47QxQ62 1nPmMnmbRR0q6GcQ3+Z8raSrBuxNDITIGtEYjULJSMa5/HzrYd1iQjAJuuPC4awh9zxXDTvm TaDqXFkg61J1ZJSkaKm4VrAnjSg4IDTSRI47RnWWWTj6R5lYImiZMqj7l2zAet8Ebt1h2Kp5 BAs8/VyJshUZX1RvERhmNkwIYw=
- Ironport-hdrordr: A9a23:JuS5VKqmdt5CoOfKtVU7aooaV5u5L9V00zEX/kB9WHVpm5Oj+v xGzc5w6farsl0ssREb9uxo9pPwJE800aQFmbX5Wo3SJzUO2VHYVb2KiLGP/9SOIU3DH4JmpM Rdmu1FeafN5DtB/LnHCWuDYrEdKbC8mcjH5Ns2jU0dKz2CA5sQkzuRYTzrdnGeKjM2Z6bQQ/ Gnl7d6TnebCD0qR/X+IkNAc/nIptXNmp6jSRkaByQ/4A3LqT+z8rb1HzWRwx9bClp0sPwf2F mAtza8yrSosvm9xBOZ/2jP765OkN+k7tdYHsSDhuUcNz2poAe1Y4ZKXaGEoVkO0amSwWdvtO OJjwYrPsx15X+UVmapoSH10w2l6zoq42+K8y7tvVLT5ejCAB4qActIgoxUNjHD7VA7gd162K VXm0qEqpt+F3r77WvAzumNcysvulu/oHIkn+JWpWdYS5EiZLhYqpFa1F9JEa0HADnx5OkcYa VT5fnnlbdrmG6hHjDkVjEF+q3uYp1zJGbKfqE6gL3a79AM90oJjXfxx6Qk7wI9HdwGOtx5Dt //Q9VVfYF1P7ErhJ1GdZc8qOuMexvwqEH3QRSvyWqOLtB1B1v977jK3Z4S2MaGPLQ18bpaou WybLofjx95R37T
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Wed, May 11, 2022 at 09:20:46AM +0200, Roger Pau Monné wrote:
> Subject line needs to be updated :).
>
> On Tue, May 10, 2022 at 05:58:23PM +0200, Marek Marczykowski-Górecki wrote:
> > Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared
> > by the PCI Local Bus Specification Revision 3.0 (from 2004) as
> > "unknown"/"no connection". Fallback to poll mode in this case.
Forgot to comment: you should also mention that this 0xff special
handling is for x86 only, other arches can use other meanings for the
INTERRUPT_LINE register.
Likely this also implies that the 0xff check should be protected by
CONFIG_X86 (albeit I think that code is already only reachable from
x86 as Arm doesn't yet enable CONFIG_PCI).
Thanks, Roger.
|