[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] xen/arm: smmu-v3: Fix MISRA C 2012 Rule 1.3 violations
- To: Xenia Ragiadakou <burzalodowa@xxxxxxxxx>
- From: Bertrand Marquis <Bertrand.Marquis@xxxxxxx>
- Date: Wed, 29 Jun 2022 07:24:36 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6EbsGJD4I+ly+24gKzUWrr0eH8sJyGBH/nl4+VcvseE=; b=Fk1LAPwKH5ZARubk4sQ760O8z5lJcdzR1lJoiZ0zHb+vtXEE9Byhl4ND2g3gBNkkkhhhLEKnitE3m5rdjQiKTyAJdNIPfX+ctwPD0eWjjfi2fKbJqkzilQS4NsaWznUI6Nr7djkCkDY0nFuNMpiv7G0LVEdHSRteUsl7fHmseu4p7Bhv+8O0dbbrYJjSC4/2LO2/go184dtIeJmV7mssxULJz79VJ/AEI/FXJVQvkEqBW9TO1zi0F7qV9FNpTpWVsfRZ1tyRhCpId1KTwIxfd0FMzL9iOCA22HWkhqPRjB802lIYsyHSJVRASVlJ8fxGUplLS1+McmdY7SLtSC197w==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6EbsGJD4I+ly+24gKzUWrr0eH8sJyGBH/nl4+VcvseE=; b=CSqeLoH9jLVjeYqELhp+XiAoukAd0CTE8IkFIp7fVoYiRjlYC/4tQIKMTnBHM3zgpySKx+WXstnW9AUnNzrVVoI2aKFQH0/vlTe80bsKT/CgGluS4A1l8PUozlMrnwIbm8pJm707GtvPipvrQWgjq+CmWwbSN0R05ucqZCPedqL23oJm8SOtcYYZUOBeHF3/oRSUcJ9Xe06/RU/6KIcRydHW/nJB/ElfkAteOf9IILpfRld8LoeAyg9RtK2w0zIvNFIgvWAgdyUFDQAQm04UUTSreswmQ++knZUUlX9fWfZMXHZchy9WGl/jMR5rWLschCnGoEJVHxEHoVRCy+ysJQ==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=InAND9r4oiv8xYPczmAnsDVVD/UtO+9ownfAFghBz/sIiywGyES3sMgvAflyEKwD+0R5w3YUag+8WJgYPk3Ty159sfL4Ibp8JP6LsQRwhErwWXHIyEQC3kkLLmfSEwwUoRkmXdNPHXobkcXGMtcM8e7Gbg1uHd0z4y+pliYOYjy+yZj7AIo2swJk+wwh1NI05FHgO76WrLI6y3k1RMKPUqpY3T0jUAg7U+mKvd2AyYenUcUdGPA2RF3V2OtJ/RIW0Zo3Pfl10lo5rKH+JoJyIdjMFq5QlgA/uyWUybOq7wrZiTbOuKjmZdHkPMw0M/CQs0ksHocosIpX4VzlR6FEYQ==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f0UBpEZVbWleMb/WwPGspq4Uk2FoOl/dO9yYMGdg+GJEd+RPFQUJKHxWtpuCVgqMirgzoEFWrx1XskoGJiEF+G05mow6l90ST8vCRIqqemZILyiOVUmcKXqDz5rQeuyhUOqcHhldpQPboeBJA/JqL+a1dc6E6tSYSCRXGBIssk5+BiIJUlbxxmvYeUo77ghXviFfLN+cZx/dtVL0qLSM3dAwgPZUJV6yAlp7nFuRmUS2luR+0MtfwNolPhwbQgIbq8wZULJTtWZFQ5hvoL8r2Jsvz5nvBRCuRV5HzmCBzd/wFsGAw1xkY3q9Q2k2P6eTh7LhUPUZSVawrtzRSMT/9Q==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Rahul Singh <Rahul.Singh@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Wed, 29 Jun 2022 07:24:59 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Thread-index: AQHYiwEFKAxihkpP+kCxp/TNi89h5q1l/I6A
- Thread-topic: [PATCH] xen/arm: smmu-v3: Fix MISRA C 2012 Rule 1.3 violations
Hi Xenia,
> On 28 Jun 2022, at 16:08, Xenia Ragiadakou <burzalodowa@xxxxxxxxx> wrote:
>
> The expression 1 << 31 produces undefined behaviour because the type of
> integer
> constant 1 is (signed) int and the result of shifting 1 by 31 bits is not
> representable in the (signed) int type.
> Change the type of 1 to unsigned int by adding the U suffix.
>
> Signed-off-by: Xenia Ragiadakou <burzalodowa@xxxxxxxxx>
> ---
> Q_OVERFLOW_FLAG has already been fixed in upstream kernel code.
> For GBPA_UPDATE I will submit a patch.
>
> xen/drivers/passthrough/arm/smmu-v3.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/xen/drivers/passthrough/arm/smmu-v3.c
> b/xen/drivers/passthrough/arm/smmu-v3.c
> index 1e857f915a..f2562acc38 100644
> --- a/xen/drivers/passthrough/arm/smmu-v3.c
> +++ b/xen/drivers/passthrough/arm/smmu-v3.c
> @@ -338,7 +338,7 @@ static int platform_get_irq_byname_optional(struct device
> *dev,
> #define CR2_E2H (1 << 0)
>
> #define ARM_SMMU_GBPA 0x44
> -#define GBPA_UPDATE (1 << 31)
> +#define GBPA_UPDATE (1U << 31)
> #define GBPA_ABORT (1 << 20)
>
> #define ARM_SMMU_IRQ_CTRL 0x50
> @@ -410,7 +410,7 @@ static int platform_get_irq_byname_optional(struct device
> *dev,
>
> #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1))
> #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift))
Could also make sense to fix those 2 to be coherent.
> -#define Q_OVERFLOW_FLAG (1 << 31)
> +#define Q_OVERFLOW_FLAG (1U << 31)
> #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG)
> #define Q_ENT(q, p) ((q)->base + \
> Q_IDX(&((q)->llq), p) * \
Cheers
Bertrand
|