[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
RE: [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs
- To: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Henry Wang <Henry.Wang@xxxxxxx>
- Date: Wed, 6 Jul 2022 07:30:11 +0000
- Accept-language: zh-CN, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=31xSZXbvdsibcVIceV39U3OFfJH3Dlf23IBPFbdbs58=; b=lyS2vpd2VgBPzWAgB9vSCU9zG5uR+Q6IO10cfHphwjx6WFuC56bFUCZJZab+uWXATNkZrgvd+xkxouSdf+rmRz7EpPC8ao1Sc9mDXRc9vHY62aV1cqV5/f1y849tG8XGlHAvCkfTsUhkTNWWf0WreVbVsYugHLps49+ScWzZ4DbHb4MHjHD7VFjVjWBxihkG5dpOysgLJ3+0pp1oWj6N1L2Bowh2udd+dVMN6CqrkAF29CbSRrGq1T7ExYWu/YA9iDTE6HZ0IHW5JT2lVGZiRymDQEvOEc5NwdLeI42oAFPJJ22zfq016QU2WZ6tc3zQvMRP6mSzGNv7tIO+d6d1ww==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=31xSZXbvdsibcVIceV39U3OFfJH3Dlf23IBPFbdbs58=; b=S9RNykFbEc9sTf0Xtr1qkGhUd7V5de2WMnmQqGTHJGxBcMOvFs/uyNz9Jcpqh/bcPrbVrfaSsJedU74ObxuYAZSM7ZV/OKp4J9MTiypxVZbK9ltRELHi7jj6Q0HNhBuYbhEAVR2h9VseBSooulKpA10RvoWpCmmm1uV6FTBsu5V05UOq0U81rF3a6Zo39vxYERQsMcMNWs9xW5907IC72xg2T7lisjV1o9iYUN7uNXQIe6Ks25LNabaxSCYMFslrzfqCD8XxmX768/tpsH5VocTK5hEvIZPXNfmbZwYlULm5p57OgU8tbqiHum/jC9SGBC+CevTyWjVhZ8DFdQD8Zg==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=K7JCNv8kjfDFqDB/FbrXx3QjZprpyktbPmp0D55zTEb1mLK3CcCfMmhmZIS7pdIubEuxCyo+IaXOZr0rG8wRFaiGR9T7KUN80qv2D1nnBqeGCKcFvCV3mY9IDT/LjooZiv4wuo9z0sT1fxV5Gr7o3jpx4bm55scQCwUny26zmkdgZvkXqM9dMlXVPqMLDCN8xBcY0JYafLPgxRqNrM6UgQ0F6J6gufQkGVtZq5/jp2SSqn4nq4cyx2zjrYq63dDgHCiIZgZSjkA5WP3SWQU64pqc+LbqYRlvemTze1nEv9Z/+YyaCc0LMnoy1EqZjiw4fxJnkyLAufVPhpa4zFffmw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ChHgcHmMM3HivrGoq8e+P0iHQ4RMiK+SdN0f/xcZADkGZeWX8kIaKUcVBYbkVZ2phSZXOI0Lx6lJwUkpewmh/Jcaux0JyuCxWAfT9dVYn4Q63zGoeCVZ4ue34Cs9gLrBHU5nES7JVlF2aBjFYISbOqp8jHENeI3SorK5qqvlVKd+sVt2Ew4r+NJHkzYl8X7mcroj9Lg0rVYtOcyAmSr4p9QqajwJioxgtYg5/CPabF/ShQD2VlFgXnAD+9AXk2xKvyaG0zOer7VmAbPeIUnwKCDiLIUaR+8cW2GhNX3rsXPbfvn5zOBc5NegsNehsCT02dWA/p7b01dxVmm1sRSe4g==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, Jun Nakajima <jun.nakajima@xxxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>
- Delivery-date: Wed, 06 Jul 2022 07:30:27 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Thread-index: AQHYbE8ENIrU0fzd30KB0FdsdC25cq1xLOqQ
- Thread-topic: [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs
Hi,
It seems that this series has been stale for more than a month, so I am sending
this email as a gentle reminder with current status:
Patch #2, #3 might need further actions from the maintainers
Patch #4 might need further actions from the author.
Patch #1 #5 has been reviewed/acked.
Kind regards,
Henry
> -----Original Message-----
> Subject: [PATCH 0/5] x86/lbr: handle lack of model-specific LBRs
>
> Hello,
>
> Intel Sapphire Rapids CPUs doesn't have model-specific MSRs, and hence
> only architectural LBRs are available.
>
> Firstly implement some changes so Xen knows how to enable arch LBRs so
> that the ler option can also work in such scenario (first two patches).
>
> The lack of model-specific LBRs also affects guests, as setting
> DEBUGCTLMSR.LBR is now ignored (value hardwired to 0, writes ignored) by
> the hardware due to the lack of model-specific LBRs. The LBR format
> reported in PERF_CAPABILITIES also need to be exposed, as that's a way
> for guests to detect lack of model-specific LBRs presence (patches 3
> and 4).
>
> Patch 5 is an indentation fix that can be merged into patch 4: done
> separately to help readability of patch 4.
>
> Thanks, Roger.
>
> Roger Pau Monne (5):
> x86/ler: use feature flag to check if option is enabled
> x86/lbr: enable hypervisor LER with arch LBR
> x86/perf: expose LBR format in PERF_CAPABILITIES
> x86/vmx: handle no model-specific LBR presence
> x86/vmx: fix indentation of LBR
>
> xen/arch/x86/hvm/vmx/vmx.c | 59 ++++++++++++++-------
> xen/arch/x86/include/asm/msr-index.h | 18 +++++++
> xen/arch/x86/msr.c | 9 ++++
> xen/arch/x86/traps.c | 29 ++++++++--
> xen/arch/x86/x86_64/traps.c | 2 +-
> xen/include/public/arch-x86/cpufeatureset.h | 3 +-
> 6 files changed, 97 insertions(+), 23 deletions(-)
>
> --
> 2.36.0
>
|
