[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v4 1/2] xen/arm: smccc: add support for SMCCCv1.2 extended input/output registers
- To: Jens Wiklander <jens.wiklander@xxxxxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Fri, 8 Jul 2022 12:01:34 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=lists.xenproject.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dkim=[1,1,header.d=arm.com] dmarc=[1,1,header.from=arm.com])
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fn1NLoRlIR8hwkspj78Ki0E2vJo8CIe6tZj3P9lPuWM=; b=Uq6vGfvihvCjn4pkSxRAlFlJTuYsL2PLqnaww+iYQUQe1eZ9/U63lytfxGmrKYKBHXhu/zSLQBXcOs3AlbMXzQo2asBVEYjgMOWz5JxzxzA2gFk2o5YDwTx2fnRB/MTfxfcbNtIUk8lqNY3pEg9pKlGzNU8UQXuRkDnAAdgg2Uiq8zBHlaeE/OiP2AcltpdJb8YPT2VCTlAqkglDPgsIGCL2rQTroM4etRlpFtSkA0PRx+VfJdDhjLkMz7+O0B0e0qNKHKZ8ceStN525fa8wqyRy05jJZ0zVixbWSRoO+DlUpQxt7RzJQkwJrBmCsilFNs3WzxP/C5lGGmb9a5yx4Q==
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fn1NLoRlIR8hwkspj78Ki0E2vJo8CIe6tZj3P9lPuWM=; b=mLZHlkb8SpiC1aUDhvNC7hX5qtHNpMWVjcNa0E77Xc1fIsQOtlEl0Ht0/SdJyJXFTxrdTjBqdPFHJYy1Nz+koSVjIP5p/al9qhXygCOTVqLqm4Vw+Sh7btQ0Ezdxe+3ZCjg1xTaU1BhePGOzoUb2dE+HxIL/2TextNEBugze5Qc5GT3bNMhbXh6aa/lCvanOP26vdS+pTGkmuFXPQ6tTlVd7dzsfYkn4trC++/BmPbj/uNkBLHK+vyAdkVzbkT0rPxulOaNxB9nDOhW1fbRqm9Np6qWG6YtG/9rR2Jqgb6aPr+GzMWLBj1wr4zwprHApWLHHexNu9NU0+vY3z3nIMA==
- Arc-seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=ndo2QfRnjdB/iZ8XhzfqDppdClJRXADr7pZcvHoBLcp0bKwtGs0CaR09iql2FUU87NT9/+uhV5KDlAK70TxAi925WaAnm/ymR9udHl4ANNznyRMqtSuDNGVI0nn5DDEYMPRHd5l97JRzRr8AjUKPzQ+Bh2+kpFTwWAzhrXUVbod1bIkXK/KFAhFWe1WUKWZdz/fmr9dICLoYAeovQMDApBM/z4Ym3saxJ3ErDxsduKOJeivoQa7V9AMmdz3oUYGj+0xb0yqcZjm9bftZk6wlnPQOw4pBs9ctyQwfB3sgqwxjTf+CWyZHz6ERRxYVHbNpr4oxi5pR/spJnoXXkaBm/A==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hP+m38EMyapIKpOhCnYJzTkmwHQapKvevJHlAUTsZh7JGDHIrFjTYgmzqTR05gBIhvq7WJPoo9hbwM5q7btooOA9ZicnAvRADlFkGnZ60rCwsNUX7irDOc3XXKysxa4sZrywb0paIDQedPgwOZBIlGNeowd5Op8e1MFgGvhRxxu9vkN3ppYO9Q7Ctrg+m3Ra1Rh2ycpj7IKLcUrcUUPXC4HxvzGa4WAbrXT5C8U5B1H6/rx9yeqxAFjDzA1eugEF48FlsSFqTAvDdZrE4GC7unvePy+VDtZ+YQa0rNjKO3d2QJejUoOHtUwmLAg57hSSQLpt6tD1OtnGsvf52Z2OrQ==
- Authentication-results-original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>
- Delivery-date: Fri, 08 Jul 2022 12:02:13 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Nodisclaimer: true
- Original-authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com;
- Thread-index: AQHYkrtluLmsjith/0ae41gwW1Q+gq10X3eA
- Thread-topic: [PATCH v4 1/2] xen/arm: smccc: add support for SMCCCv1.2 extended input/output registers
Hi Jens,
> On 22 Jun 2022, at 14:42, Jens Wiklander <jens.wiklander@xxxxxxxxxx> wrote:
>
> SMCCC v1.2 AArch64 allows x0-x17 to be used as both parameter registers
> and result registers for the SMC and HVC instructions.
>
> Arm Firmware Framework for Armv8-A specification makes use of x0-x7 as
> parameter and result registers.
>
> Let us add new interface to support this extended set of input/output
> registers.
>
> This is based on 3fdc0cb59d97 ("arm64: smccc: Add support for SMCCCv1.2
> extended input/output registers") by Sudeep Holla from the Linux kernel
>
> The SMCCC version reported to the VM is bumped to 1.2 in order to support
> handling FF-A messages.
>
> Signed-off-by: Jens Wiklander <jens.wiklander@xxxxxxxxxx>
> ---
>
I think you need to update the copyright information of the smccc.h header
(maintainers can confirm if it’s needed),
also it seems that you agreed with Julien to update the commit message with a
reference to the spec but maybe you
forgot about that:
https://patchwork.kernel.org/comment/24897413/
With these addressed:
Reviewed-by: Luca Fancellu <luca.fancellu@xxxxxxx>
|
