[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH] x86/msr: fix X2APIC_LAST
- To: <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Edwin Török <edvin.torok@xxxxxxxxxx>
- Date: Tue, 26 Jul 2022 15:43:36 +0100
- Authentication-results: esa3.hc3370-68.iphmx.com; dkim=none (message not signed) header.i=none
- Cc: Edwin Török <edvin.torok@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
- Delivery-date: Tue, 26 Jul 2022 14:44:16 +0000
- Ironport-data: A9a23:hTtjr6pVw5ACCCxTVd5RBq+9RR5eBmJ0ZRIvgKrLsJaIsI4StFCzt garIBmDM66LY2ujL953aYm0oEgHvsLRy99kQAs/pS1gRCka9ZuZCYyVIHmrMnLJJKUvbq7GA +byyDXkBJppJpMJjk71atANlVEliefSAOKU5NfsYkhZXRVjRDoqlSVtkus4hp8AqdWiCkaGt MiaT/f3YTdJ4BYpdDNPg06/gEk35q6q52lF5gZWic1j5zcyqVFEVPrzGonpR5fIatE8NvK3Q e/F0Ia48gvxl/v6Ior4+lpTWhRiro/6ZWBiuFIPM0SRqkEqShgJ+rQ6LJIhhXJ/0F1lqTzTJ OJl7vRcQS9xVkHFdX90vxNwS0mSNoUekFPLzOTWXWV+ACQqflO1q8iCAn3aMqU89vhpE1EWr ccaFw4hRRWFl/CU+O60H7wEasQLdKEHPasas3BkizrYEewnUdbIRKCiCd1whWlqwJoURLCHO pRfOWEHgBfoOnWjPn8aBIw/mqG0gWP4cBVTqU6PpLpx6G/WpOB0+OezboeKKobXLSlTtmG9n D/5xEbbOzhZFcLHmAvG8y6OhvCayEsXX6pNTeblp5aGmma72Wg7GBAQE1yhrpGRiESzRtZeI Ew84Tc1oO4580nDZsnwWVi0rWCJujYYWsFMCKsq5QeV0K3W7g2FQG8eQVZ8hMcO7ZFsA2Zwj xnQwo2vVWcHXKCppWy10ruKsyGCYXAuL1A8SQQBSxsXweG/r9Rm5v7QdeqPAJJZn/WsR2ygk 2jS9nNn71kApZVVjvvmpDgrlxrp/8GUFVBtu207S0r/tmtEiJiZi5tEALQxxdJJN86nQ1aIp xDocODOvblVXflheMFgKdjh/Y1FBN7faVUweXY1Q/EcG82FohZPh7x47jBkP1tOOc0ZYzLva 0K7kVoPuc8MYyfzPf8oPtzZ5yEWIU/ITI+NaxwpRoAWPsgZmPGvp0mCmnJ8L0iyyRNxwMnTy L+QcNq2DGZyNJmLOAGeHr5FuZd2l39W+I8mbcqkp/hR+ebBOSX9pHZsGAfmU93VG4vf+F+Lq YkOaprVo/idOcWnChTqHUcoBQhiBRAG6Vre8qS7qsbrztJaJVwc
- Ironport-hdrordr: A9a23:VkYgAaGQmTti8n8HpLqE5MeALOsnbusQ8zAXP0AYc3Jom6uj5q eTdZUgpHvJYVkqOE3I9ertBEDiewK4yXcW2/hzAV7KZmCP0wHEEGgL1/qF/9SKIUzDH4Bmup uIC5IOauHNMQ==
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
The latest Intel manual now says the X2APIC reserved range is only
0x800 to 0x8ff (NOT 0xbff). The AMD manual documents 0x800-0x8ff too.
There are non-X2APIC MSRs in the 0x900-0xbff range now:
e.g. 0x981 is IA32_TME_CAPABILITY, an architectural MSR.
The new MSR in this range appears to have been introduced in Icelake,
so this commit should be backported to Xen versions supporting Icelake.
Backport: 4.13+
Signed-off-by: Edwin Török <edvin.torok@xxxxxxxxxx>
---
xen/arch/x86/include/asm/msr-index.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/x86/include/asm/msr-index.h
b/xen/arch/x86/include/asm/msr-index.h
index 8cab8736d8..1a928ea6af 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -148,7 +148,7 @@
#define MSR_INTERRUPT_SSP_TABLE 0x000006a8
#define MSR_X2APIC_FIRST 0x00000800
-#define MSR_X2APIC_LAST 0x00000bff
+#define MSR_X2APIC_LAST 0x000008ff
#define MSR_X2APIC_TPR 0x00000808
#define MSR_X2APIC_PPR 0x0000080a
--
2.34.1
|
