[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2] x86/msr: fix X2APIC_LAST
- To: Edwin Török <edvin.torok@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 26 Jul 2022 17:33:00 +0200
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=jznMdVRgf2kH4jvT2e7CgJ2TFLUs6FjzqKhnCeI0niw=; b=Jgp3J7AsJ5F9T1sNpwSU3S86oUX7Z5FIkaJe0cZbFXsPm6Xavfe0eA6L3W6IAMxtEJiYIKR5/RfYDQEpwDlEIcdSSn1n7MAXilv8cL2imsbcx+D++aKYJkhsX/qBKZOhtD9yw4gWlVeEkMhMiuXfjVv3YjE4oO4q2mga9eZ6DRanOcs1lwBUUEWFq4YM9WRYPoFSWc55Bmi6LKyuE5PwGJHojFL1FwotE5Y+gijTQaiUebs7t1Z3mYtNjhTUzra30nSad84HcSOm/4hnCHVmTDXtvLoMJ2SHDzYiQ+pkdNhkU9iIwCctCl37z7qYlwMow3Vbb9HC3280iVKoi6X07g==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LV4URFKUZWpJVpX32TVEFqsK7jp/GHnB2LDcR4h8eFoGeYskvyGG54M2Ht1RyLq0wwDrZifuOQPrMVC1PKqd7Ra/on80elIgLNIYXQXYIId3PQCQGB2hySZvAAf096LwRaAwTBBD9XIniWfjI4Mi9KmREbq7HFYf3ySPqbDyEj98GBb1KVZinoc1Zwz2ndQ5oqcn/byXcZNSnm0MbcfCoRRfHZIX33ILvfmPtmdWFzkPgPoHIYwzaNgEFpF9R47KYPgOhc03hdQg9BhVuzI2UIqnLbqR9hpAmv2KbRcwbEd76ojYcMaZWy/s7l5NOo3VDk30rw0n5x6XAYVDJ7oMEQ==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com;
- Cc: Jun Nakajima <jun.nakajima@xxxxxxxxx>, Kevin Tian <kevin.tian@xxxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- Delivery-date: Tue, 26 Jul 2022 15:33:07 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 26.07.2022 17:28, Edwin Török wrote:
> The latest Intel manual now says the X2APIC reserved range is only
> 0x800 to 0x8ff (NOT 0xbff).
> This changed between SDM 68 (Nov 2018) and SDM 69 (Jan 2019).
> The AMD manual documents 0x800-0x8ff too.
>
> There are non-X2APIC MSRs in the 0x900-0xbff range now:
> e.g. 0x981 is IA32_TME_CAPABILITY, an architectural MSR.
>
> The new MSR in this range appears to have been introduced in Icelake,
> so this commit should be backported to Xen versions supporting Icelake.
>
> Backport: 4.13+
FAOD nevertheless it'll be applied only back to 4.15.
> Signed-off-by: Edwin Török <edvin.torok@xxxxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
|