[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [XEN v1] xen: arm: Check if timer is enabled for timer irq


  • To: Julien Grall <julien@xxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
  • From: Ayan Kumar Halder <ayankuma@xxxxxxx>
  • Date: Wed, 10 Aug 2022 15:00:28 +0100
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8yY7vDxjFLB6kOsgaG/z9kS3VErJMPVY9qUqtOxSxyk=; b=ERQNKQ1Avegt/0hUVVIjg0PNfmAgpIRWpdlcKKXKX31yiCwxGB8UavLUQDcvuMehwGxtLnepfi/Ux9/1klPmSWLHDbEBrvhl5Djgv3ZrFq3ujwX4qyFokzu+xSt49PocaY9NNdvRxb7HSNaXAwwCUAVp4q8cDAQq0eZL0NAaApaEyJEoJlYmgOl/T3KnYZZN1SNPbQVvbsQMRTUQ8+ei+c83Zire9hMaNF3DKGJn+QwOMY9FP12c7YhZcMJtHjWWAVj0NeTognVUh5Fw2OmpAMhKdHcx6tz/tALAHgN2wEFslK+dOzUxQzWzL7SYn1aDvnbNse4JZeTup26c1MOqzA==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aAJhSTT/VxUPzo4y9WtVasQo/Qpv9pGalAACxJ+1cEgdttO33IYMaBXJBQTpqvQ2VLREvxdHGOA8mc/u6aezf4+sHXCSWuo5tF5/ZWT4PZbusGW0QrgFIvnasPKVtyBzz6Yb1qzZUTIJWnkgMVZFV6/dR5DYxZf9ANSBargprnFstYZHKeW8VtCqWja586LLMlrLYNmYCsNuyjtwUvL7TUaiTwwF485paNb33MiPwvRoc0l7RRAkfoWkaxlFpwTW4Ic9mYyXwPSs1X78yrmDL8cNb4U0AMLIP8RveqKEquMFZurttj93vy5kCEEF9qLrqSGpeA+fmWnxy2Jol4BNng==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com;
  • Cc: sstabellini@xxxxxxxxxx, stefanos@xxxxxxx, Volodymyr_Babchuk@xxxxxxxx, bertrand.marquis@xxxxxxx
  • Delivery-date: Wed, 10 Aug 2022 14:00:44 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>


On 10/08/2022 14:34, Julien Grall wrote:
Hi Ayan,
Hi Julien,

Bertrand already made some comments. I will try to avoid repeating the
same comments.

On 10/08/2022 11:58, Ayan Kumar Halder wrote:
Refer "Arm Architecture Registers DDI 0595", AArch32 system registers,

You are modifying code that is common between AArch64 and AArch32. So I would mention this behavior is common. Also, please specify the version
of the spec. This helps in case the behavior has changed.
ack

Also, NIT: I would prefer if you quote the Arm Arm rather than auxiliary
specifications.
ack

CNTHP_CTL :- "When the value of the ENABLE bit is 1, ISTATUS indicates
whether the timer condition is met."

I think the key point here is the field ISTATUS is "unknown" when the ENABLE bit is 0.
yes, this is the key thing.


Also similar description applies to CNTP_CTL as well.

One should always check that the timer is enabled and status is set, to
determine if the timer interrupt has been generated.

I understand the theory. In practice, I am not sure this could ever happen because the timer interrupt is level and by clearing *_CTL you will lower the line and therefore you should not receive the interrupt again.

Checking the 'enable' is not going to add too much overhead. So I am fine if this is added. That said, would you be able to provide more details on how this was spotted?

This was spotted while debugging an unrelated problem while porting Xen on R52. For a different reason, I was not able to get context switch to work correctly.

When I was scrutinizing the timer_interrupt() with the documentation, I found that we are not checking ENABLE.

Although the code works fine today (on aarch32 or aarch64), I thought it is better to add the check for the sake of compliance with the documentation.

I can send the v2 patch (addressing yours and Bertrand's comment) if you think it is fine.

- Ayan


Cheers,




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.