[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 05/11] x86emul: handle AVX512-FP16 fma-like insns


  • To: Jan Beulich <jbeulich@xxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
  • From: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
  • Date: Wed, 10 Aug 2022 18:14:25 +0000
  • Accept-language: en-GB, en-US
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mo4QdnL8Asg/l2cDu1TAiBlnUnWRxIQ963jSg+8Dnt0=; b=HZOCHq0/HatIKW0xXYnoOIvaxsI1rAD1oOdkJ1AKJgjI22jh2IF0F0P7CrC56B/tg1FoxLSLGpeBY00m1FSLEYvWZPUlSzpcSB3KPyvFW7xwKNI+n6G/BbqxZRxez3i/Bhj3NT4ggVTnk3W/A5ZfImFVSqomtCUV9Dc1HhXlKsdfWUyi3uwiSVYvAgjvW/G8J9QbuBB6MQSU2/tUEUOtuzCzV2CfXEkgre9/zefkPi91iNJSv1DLoU4UkSHFf9liHlcO0qzDCQLqTJ0wlZgXOQ9LO1ym9+3zHtYheC47K4WWTlC9iqNict+QVtXDGVjUeyTd+9Wo/9WQLQWkxVe/5A==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=RpQLvtsoI330uS2GWtk4R8a81/oQS94Bf/mP/EsNdAxonI8DMJkpZ+nIXsFFGeS93XRGoAtl93kZSm/+DMBJJZAyU3kbMHq6Hfi5yUMnIrB2yqkjgnB7BoxoHm+9+fSXdhWqFjw+NvRczqfOG+64prHjZcp2uN8Y1tbSOfxGOzTpXZpy7qvf8Hp/WgptnSRURlGPddz4vQVH6HeBKsS51EULQSXBOCHfSfE6c1b/h4+6RkQmIMoWQLp+bcX2K8DphCiRNb9gnTMxkkFDZVk8YyJc7wa3DSDSJohdWqA+40wswwlq3USwWdskNVPuNraN2LZNPuh3Jb96ANu2oU77pQ==
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
  • Cc: Wei Liu <wl@xxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>
  • Delivery-date: Wed, 10 Aug 2022 18:14:39 +0000
  • Ironport-data: A9a23:th0aIKu7VZ9S5qIT1rapUbm/w+fnVE9fMUV32f8akzHdYApBsoF/q tZmKWDXafiLamb1Kd5wOYSyoEIFv8WAy9dqSQJvr300Hy5D+JbJXdiXEBz9bniYRiHhoOOLz Cm8hv3odp1coqr0/0/1WlTZhSAgk/vOHtIQMcacUghpXwhoVSw9vhxqnu89k+ZAjMOwRgiAo rsemeWGULOe82MyYzl8B56r8ks15qyi4WtA5TTSWNgQ1LPgvyhNZH4gDfnZw0vQGuF8AuO8T uDf+7C1lkuxE8AFU47Nfh7TKyXmc5aKVeS8oiM+t5uK23CukhcawKcjXMfwXG8M49m/c3Kd/ /0W3XC4YV9B0qQhA43xWTEAe811FfUuFLMqvRFTGCFcpqHLWyKE/hlgMK05FZAh37Y0Am1Nz 9EZBiIXTgyct+eG3K3uH4GAhux7RCXqFKU2nyg5iBr+VLMhS52FRLjW79hF2jt2ntpJAfvVe 8seb3xocQjEZBpMfFwQDfrSns/x3iW5L2Ie9QzT/PVti4TQ5FUZPLzFGdzZYNGVA+5SmV6Vv Dnu9GXlGBAKcteYzFJp91rz2b+XzHyrBur+EpWgz+Bl3maey1cwI0crVhjmgt3jlWSHDoc3x 0s8v3BGQbIJ3E6hQ8T5Xha4iGWZpRNaUN1Ve8Uq5QfIxqfK7gKxAmkfUiUHeNEgrNUxRzEhy hmOhdyBLSNrmK2YTzSa7Lj8kN+pES0cLGtHbihdSwIAuoDnuNtq0UiJSct/GqmoiNGzASv33 z2BsCk5gfMUkNIP0KK4u1vAhlpAu6T0c+L83S2PNkrN0++zTNfNi1CAgbQD0ct9EQ==
  • Ironport-hdrordr: A9a23:6ttC1qwf/MQZynE6EsMtKrPxBOgkLtp133Aq2lEZdPULSKGlfp GV9sjziyWetN9IYgBapTiBUJPwIk81bfZOkMQs1MSZLXPbUQyTXc1fBOrZsnfd8kjFmtK1up 0QFJSWZOeQMbE+t7eD3ODaKadu/DDkytHPuQ629R4EIm9XguNbnn5E422gYy9LrXx9dP4E/e 2nl696TlSbGUg/X4CePD0oTuLDr9rEmNbPZgMHPQcu7E2jnC6l87nzFjmfx1M7XylUybkv3G DZm0ihj5/T8s2T+1v57Sv+/p5WkNzuxp9qA9GNsNEcLnHBmxulf4NoXpyFpXQQrPu04Fgnvd HQq1MLPth16VnWYmapyCGdlTXI4XIL0TvP2FWYiXzsrYjSXzQhEfdMgopfb1/w91cglMsU6t MJ40up875sST/QliX04NbFEztwkFCvnHYkmekPy1RCTIolbqNLp4B3xjIWLH5AJlO+1GkUKp goMCju3ocRTbpcVQGBgoBb+q3pYp30JGbffqFNgL3P79EcpgEF86JR/r1iop5HzuN8d3AM3Z W7Dkwj/os+MfM+fOZzAvwMTtCwDXGISRXQMHiKKVCiD60fPWnRwqSHqYndydvaD6Dg9qFC7q jpQRddryo/akjuAcqB0NlC9Q3MWny0WXDoxttF75Z0t7XgTP6zWBfzA2wGgo+lubESE8fbU/ G8NNZfBOLiN3LnHcJM0xflU5dfJHECWIkeu8o9WViJvsXXQ7ea/tDzYbLWPv7gADwkUmTwDj 8KWyXyPtxJ6gSxVnrxkHHqKgfQk4zEjOdN+YThjpguIdI2R/xxWyAu+CeEz9DOLyFeuaore0 Y7KK/7k8qA1BuLwVo=
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
  • Thread-index: AQHYgKLMYZVUVS03kE6CW6Ot9D+s3a2oyMWA
  • Thread-topic: [PATCH 05/11] x86emul: handle AVX512-FP16 fma-like insns

On 15/06/2022 11:28, Jan Beulich wrote:
> The Map6 encoding space is a very sparse clone of the "0f38" one. Once
> again re-use that table, as the entries corresponding to invalid opcodes
> in Map6 are simply benign with simd_size forced to other than simd_none
> (preventing undue memory reads in SrcMem handling early in
> x86_emulate()).

Again, this needs communicating in the code.

>
> Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx>
>
> --- a/xen/arch/x86/x86_emulate/decode.c
> +++ b/xen/arch/x86/x86_emulate/decode.c
> @@ -1231,6 +1231,16 @@ int x86emul_decode(struct x86_emulate_st
>                          d = twobyte_table[b].desc;
>                          s->simd_size = twobyte_table[b].size ?: simd_other;
>                          break;
> +
> +                    case evex_map6:
> +                        if ( !evex_encoded() )
> +                        {
> +                            rc = X86EMUL_UNRECOGNIZED;
> +                            goto done;
> +                        }
> +                        opcode |= MASK_INSR(6, X86EMUL_OPC_EXT_MASK);
> +                        d = twobyte_table[0x38].desc;

So the manual says that map spaces 2, 3, 5 and 6 are regular maps (insn
length doesn't depend on the opcode byte), with map 3 being the only one
which takes an imm byte.

I think this means that SrcImm and SrcImmByte will cause x86_decode() to
get the wrong instruction length.

> +                        break;
>                      }
>                  }
>                  else if ( s->ext < ext_8f08 + ARRAY_SIZE(xop_table) )
> @@ -1479,6 +1489,24 @@ int x86emul_decode(struct x86_emulate_st
>              disp8scale = decode_disp8scale(twobyte_table[b].d8s, s);
>              break;
>  
> +        case ext_map6:
> +            d = ext0f38_table[b].to_mem ? DstMem | SrcReg
> +                                        : DstReg | SrcMem;
> +            if ( ext0f38_table[b].two_op )
> +                d |= TwoOp;

... but here we discard the table desc and construct it from first
principles.

Why are we processing it twice?

~Andrew

 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.