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Re: [PATCH 2/2] x86/spec-ctrl: Reduce HVM RSB overhead where possible
- To: Jason Andryuk <jandryuk@xxxxxxxxx>
- From: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
- Date: Thu, 11 Aug 2022 17:05:17 +0000
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- Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Jan Beulich <JBeulich@xxxxxxxx>, Roger Pau Monne <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>
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- Thread-topic: [PATCH 2/2] x86/spec-ctrl: Reduce HVM RSB overhead where possible
On 09/08/2022 21:20, Jason Andryuk wrote:
> On Tue, Aug 9, 2022 at 1:01 PM Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> wrote:
>> diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
>> index 17e103188a53..8a6a5cf20525 100644
>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> @@ -3934,8 +3934,24 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs)
>> {
>> unsigned long exit_qualification, exit_reason, idtv_info, intr_info = 0;
>> unsigned int vector = 0, mode;
>> - struct vcpu *v = current;
>> - struct domain *currd = v->domain;
>> + struct vcpu *v;
>> + struct domain *currd;
>> +
>> + /*
>> + * To mitigate Post-Barrier RSB speculation, we must force one CALL
>> + * instruction to retire before letting a RET instruction execute.
> I think it would be clearer if this comment mentioned LFENCE like the
> commit message does. Looking at this change without the commit
> message the connection is not obvious to me at least. Maybe "we must
> force one CALL instruction to retire (with LFENCE) before letting a
> RET instruction execute"?
While I'm sympathetic to trying to make this easier to follow, throwing
extra LFENCE's around isn't the right way forward IMO.
LFENCE *is* the basis of a lot of software mitigations, because it has
been specified by Intel and AMD to also be a dispatch barrier.
This has been covered in multiple whitepapers from both vendors, and has
been updated in the main manuals for 4 years or now now.
~Andrew
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