Re: [PATCH 00/12] Arm cache coloring

[Julien Grall <julien@xxxxxxx>]

Hi Carlo,

On 26/08/2022 13:50, Carlo Nonato wrote:
> Shared caches in multi-core CPU architectures represent a problem for
> predictability of memory access latency. This jeopardizes applicability
> of many Arm platform in real-time critical and mixed-criticality
> scenarios. We introduce support for cache partitioning with page
> coloring, a transparent software technique that enables isolation
> between domains and Xen, and thus avoids cache interference.
>
> When creating a domain, a simple syntax (e.g. `0-3` or `4-11`) allows
> the user to define assignments of cache partitions ids, called colors,
> where assigning different colors guarantees no mutual eviction on cache
> will ever happen. This instructs the Xen memory allocator to provide
> the i-th color assignee only with pages that maps to color i, i.e. that
> are indexed in the i-th cache partition.
>
> The proposed implementation supports the dom0less feature.
> The solution has been tested in several scenarios, including Xilinx Zynq
> MPSoCs.
>
> Overview of implementation and commits structure
> ------------------------------------------------
>
> - [1-3] Coloring initialization, cache layout auto-probing and coloring
>    data for domains are added.
> - [4-5] xl and Device Tree support for coloring is addedd.
> - [6-7] A new page allocator for domain memory that implement the cache
>    coloring mechanism is introduced.
> - [8-12] Coloring support is added for Xen .text region.
>
> Changes in v2
> -------------
>
> Lot of things changed between the two versions, mainly I tried to follow
> all the comments left by the maintainers after the previous version review.
> Here is a brief list of the major points (even if, imho, it's easier to
> repeat all the review process):
The series doesn't build on Arm64 without cache coloring. Please make 
sure to compile and check that Xen still boot on system after your 
series with cache coloring disabled.
Cheers,

--
Julien Grall