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Re: Crash when writing to x86 hardware debug registers
- To: Neil Sikka <neilsikka@xxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Fri, 16 Sep 2022 08:14:41 +0200
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- Cc: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Fri, 16 Sep 2022 06:14:52 +0000
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On 15.09.2022 22:04, Neil Sikka wrote:
> Update: I rebuilt the hypervisor binary in debug mode and get the following
> output in xl dmesg after the crash.
>
> (XEN) HVM9 restore: CPU 0
> (XEN) HVM9 restore: PIC 0
> (XEN) HVM9 restore: PIC 1
> (XEN) HVM9 restore: IOAPIC 0
> (XEN) HVM9 restore: LAPIC 0
> (XEN) HVM9 restore: LAPIC_REGS 0
> (XEN) HVM9 restore: PCI_IRQ 0
> (XEN) HVM9 restore: ISA_IRQ 0
> (XEN) HVM9 restore: PCI_LINK 0
> (XEN) HVM9 restore: PIT 0
> (XEN) HVM9 restore: RTC 0
> (XEN) HVM9 restore: HPET 0
> (XEN) HVM9 restore: PMTIMER 0
> (XEN) HVM9 restore: MTRR 0
> (XEN) HVM9 restore: VIRIDIAN_DOMAIN 0
> (XEN) HVM9 restore: CPU_XSAVE 0
> (XEN) HVM9 restore: VIRIDIAN_VCPU 0
> (XEN) HVM9 restore: VMCE_VCPU 0
> (XEN) HVM9 restore: TSC_ADJUST 0
> (XEN) HVM9 restore: CPU_MSR 0
> (XEN) d9: VIRIDIAN MSR_TIME_REF_COUNT: accessed
> (XEN) vmx.c:3295:d9v0 RDMSR 0x00000000 unimplemented
Now that's MSR_P5_MC_ADDR, and hence an issue which Roger did already see
and fix. You will want to update to 4.16.2.
Jan
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