Re: Need guidance to support reading GICR_TYPER (64 bit register) on Aarch32_v8r

[Julien Grall <julien@xxxxxxx>]

On 13/10/2022 12:47, Ayan Kumar Halder wrote:
> Hi Arm mantainers/Folks,
Hello,

> Please refer to the discussion 
> https://github.com/zephyrproject-rtos/zephyr/pull/51163 .
> We intend to run Zephyr as a domU guest on Xen on Aarch32_v8R fixed 
> virtual platform.
> Zephyr is trying to read GICR_TYPER which is a 64 bit register using 
> ldrd instruction.
> As GICR is emulated by Xen, so this instruction gets trapped with HSR = 
> 0x9200000c.
> As ISV is 0, so Xen cannot emulate this instruction.
>
> The proposed solution is to use two sys_read32() on GICR_TYPER to return 
> the lower and upper 32 bits.
> With this, HSR = 0x9383 000c, ISV=1 so ISS is valid.
>
> Now, for Xen to emulate this read, I have proposed the modifications (in 
> my last comment).
I am confused. Looking at the emulation of GICR_TYPER in Xen 
(arch/arm/vgic-v3.c), the code should already be able to handle 32-bit 
access.
I doesn't look like we need to modify Xen. What did I miss?

Cheers,

--
Julien Grall