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GICv3: Aarch32: Need guidance on the atomic access of "union host_lpi" or if ITS is supported on R52
- To: Andre Przywara <andre.przywara@xxxxxxx>, "stefanos@xxxxxxxxxx" <stefanos@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, bertrand Marquis <Bertrand.Marquis@xxxxxxx>, "Volodymyr_Babchuk@xxxxxxxx" <Volodymyr_Babchuk@xxxxxxxx>
- From: Ayan Kumar Halder <ayankuma@xxxxxxx>
- Date: Tue, 25 Oct 2022 13:25:52 +0100
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- Delivery-date: Tue, 25 Oct 2022 12:26:20 +0000
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Hi Andre/All,
This came up while porting Xen on R52.
Refer "ARM DDI 0568A.cID110520", B1.3.1
"A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE
must not implement LPI support. "
Does this mean ITS is not supported on R52 ? I am assuming yes, please
correct me if mistaken.
If the answer is no, then my next query is follows :-
diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
index 9ca74bc321..dea60aac0d 100644
--- a/xen/arch/arm/gic-v3-lpi.c
+++ b/xen/arch/arm/gic-v3-lpi.c
@@ -423,7 +423,7 @@ int gicv3_lpi_init_host_lpis(unsigned int host_lpi_bits)
int rc;
/* We rely on the data structure being atomically accessible. */
- BUILD_BUG_ON(sizeof(union host_lpi) > sizeof(unsigned long));
+ BUILD_BUG_ON(sizeof(union host_lpi) > sizeof(uint64_t));
"unsigned long" on Aarch32 is 32 bits. So this bug gets triggered.
Is it fine to change it as above ?
Reading"ARM DDI 0487G.bID07202", E2.2.1, "Requirements for single-copy
atomicity".
"LDRD and STRD accesses to 64-bit aligned locations are 64-bit
single-copy atomic as seen by translation table walks and accesses to
translation tables"
Does this imply that atomicity will be retained (with the above change)
? Os will this require ldrexd/strexd as R52 supports MPU (not MMU, so
translation tables are irrelevant).
Kind regards,
Ayan
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