Re: [XEN v4] xen/arm: vGICv3: Emulate properly 32-bit access on GICR_PENDBASER

[Julien Grall <julien@xxxxxxx>]

On 27/10/2022 16:40, Ayan Kumar Halder wrote:
> On 27/10/2022 10:44, Andre Przywara wrote:
> > On Wed, 26 Oct 2022 19:30:04 +0100
> > Ayan Kumar Halder <ayankuma@xxxxxxx> wrote:
> >
> > Hi,
> Hi Andre,
Hi,

> I need a clarification.
I am not Andre but will answer :).

[...]

> > >           /* Writing PENDBASER with LPIs enabled is UNPREDICTABLE. */
> > >           if ( !(v->arch.vgic.flags & VGIC_V3_LPIS_ENABLED) )
> > >           {
> > > -            reg = v->arch.vgic.rdist_pendbase;
> > > +            reg = read_atomic(&v->arch.vgic.rdist_pendbase);
> > >               vreg_reg64_update(&reg, r, info);
> > >               reg = sanitize_pendbaser(reg);
> > > -            v->arch.vgic.rdist_pendbase = reg;
> > > +            write_atomic(&v->arch.vgic.rdist_pendbase, reg);
> > >           }
> > > -        spin_unlock_irqrestore(&v->arch.vgic.lock, false);
> Shouldn't this be "spin_unlock_irqrestore(&v->arch.vgic.lock, flags)" ?
Good catch. Yes it does. The current code will clear DAIF (even if 
irqsave touch only I). The I/O emulation is done with interrupts enabled 
usually, so now they are going to be unhandled until 
leave_hypervisor_to_guest().
This could be a "very" long time. Thankfully ITS is experimental, 
otherwise I would have considered this a potential security issue.
Can you send a separate patch for that?

Cheers,

--
Julien Grall