Re: [XEN v2 12/12] xen/Arm: GICv3: Enable GICv3 for AArch32

[Julien Grall <julien@xxxxxxx>]

Hi Ayan,

On 31/10/2022 15:13, Ayan Kumar Halder wrote:
> Refer ARM DDI 0487G.b ID072021,
> D13.2.86 -
> ID_PFR1_EL1, AArch32 Processor Feature Register 1
>
> GIC, bits[31:28] == 0b0001 for GIC3.0 on Aarch32
>
> One can now enable GICv3 on AArch32 systems. However, ITS is not supported.
s/enable/use/

> The reason being currently we are trying to validate GICv3 on an AArch32_v8R
> system. Refer ARM DDI 0568A.c ID110520, B1.3.1,
> "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not
> implement LPI support."
>
> Updated SUPPORT.md.
>
> Signed-off-by: Ayan Kumar Halder <ayankuma@xxxxxxx>
> ---
>
> Changed from :-
> v1 - 1. Remove "ARM_64 || ARM_32" as it is always true.
> 2. Updated SUPPORT.md.
>
>   SUPPORT.md                            | 6 ++++++
>   xen/arch/arm/Kconfig                  | 4 ++--
>   xen/arch/arm/include/asm/cpufeature.h | 1 +
>   3 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/SUPPORT.md b/SUPPORT.md
> index cf2ddfacaf..0137855c66 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -82,6 +82,12 @@ Extension to the GICv3 interrupt controller to support MSI.
>   
>       Status: Experimental
>   
> +### ARM/GICv3 + AArch32 ARM v8
The general apprpoach in SUPPORT.MD is to name the feature and then 
describe per arch the exact support. For this case it would be:
## ARM/GICv3

GICv3 is an interrupt controller specification designed by Arm.

Status, Arm64: Security supported
Status, Arm32: Supported, not security supported

Cheers,

--
Julien Grall